PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 400

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
Timing Diagrams and Specifications
DS39635B-page 398
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 365
Transition for Entry to PRI_IDLE Mode ...................... 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 44
Transition for Wake from Sleep (HSPLL) ................... 43
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 42
USART Synchronous Receive (Master/Slave) ........ 375
USART Synchronous Transmission
A/D Conversion Requirements ................................ 377
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 361
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 359
I
I
2
2
C Bus Data Requirements (Slave Mode) .............. 372
C Bus Start/Stop Bits Requirements
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 281
PRI_RUN Mode ................................................. 42
PRI_RUN Mode (HSPLL) .................................. 41
(Master/Slave) .................................................. 375
Internal RC Accuracy ....................................... 360
(All CCP Modules) ........................................... 366
(Master Mode, CKE = 0) .................................. 367
(Master Mode, CKE = 1) .................................. 368
(Slave Mode, CKE = 0) .................................... 369
(CKE = 1) ......................................................... 370
(Slave Mode) .................................................... 371
DD
DD
) ........................................... 55
, V
DD
DD
DD
, Case 1) ....................... 54
, Case 2) ....................... 54
Rise T
PWRT
) .............. 54
Preliminary
Top-of-Stack Access .......................................................... 64
TRISE Register
TSTFSZ ........................................................................... 327
Two-Speed Start-up ................................................. 271, 281
Two-Word Instructions
TXSTA1 Register
TXSTA2 Register
V
Voltage Reference Specifications .................................... 355
W
Watchdog Timer (WDT) ........................................... 271, 279
WCOL ...................................................... 197, 198, 199, 202
WCOL Status Flag ................................... 197, 198, 199, 202
WWW Address ................................................................ 399
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 327
XORWF ........................................................................... 328
Master SSP I
Master SSP I
PLL Clock ................................................................ 360
Program Memory Read Requirements .................... 362
Program Memory Write Requirements .................... 363
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
USART Synchronous Receive Requirements ......... 375
USART Synchronous Transmission
PSPMODE Bit .......................................................... 140
Example Cases .......................................................... 68
BRGH Bit ................................................................. 213
BRGH Bit ................................................................. 234
Associated Registers ............................................... 280
Control Register ....................................................... 279
During Oscillator Failure .......................................... 282
Programming Considerations .................................. 279
Requirements .................................................. 373
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 364
Requirements .................................................. 365
Requirements .................................................. 375
2
2
C Bus Data Requirements ................ 374
C Bus Start/Stop Bits
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