PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 98

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
7.3
The external memory interface implemented in
PIC18F6410 devices operates only in Multiplexed 8-bit
mode; data shares the 8 Least Significant bits of the
address bus.
Figure 7-1 shows an example of 8-bit Multiplexed
mode for PIC18F8310/8410 devices. This mode is
used for a single 8-bit memory connected for 16-bit
operation. The instructions will be fetched as two 8-bit
bytes on a shared data/address bus. The two bytes are
sequentially fetched within one instruction cycle (T
Therefore, the designer must choose external memory
devices according to timing calculations based on 1/2
T
speed selection, glue logic propagation delay times
must be considered along with setup and hold times.
FIGURE 7-7:
DS39635A-page 96
CY
(2 times the instruction rate). For proper memory
8-Bit Mode
Note 1:
PIC18F8410
8-BIT MULTIPLEXED MODE EXAMPLE
AD<15:8>
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
A<19:16>
AD<7:0>
WRL
ALE
BA0
CE
OE
CY
Preliminary
).
373
The Address Latch Enable (ALE) pin indicates that the
address bits A<15:0> are available on the external
memory interface bus. The Output Enable signal (OE)
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing; it is inactive
(asserted high) whenever the device is in Sleep mode.
This generally includes basic EPROM and Flash devices.
It allows table writes to byte-wide external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate level of the BA0
control line is strobed on the LSb of the TBLPTR.
D<7:0>
A<19:0>
D<15:8>
Address Bus
Data Bus
Control Lines
 2004 Microchip Technology Inc.
A0
A<x:1>
D<7:0>
CE
OE
WR
(1)