PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 229

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA1<5>), or the Continuous Receive
Enable bit, CREN (RCSTA1<4>). Data is sampled on
the RX1 pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 17-13:
TABLE 17-8:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA1
RCREG1
TXSTA1
BAUDCON1 ABDOVF
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
RC6/TX1/CK1 pin
RC6/TX1/CK1 pin
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Name
Initialize the SPBRGH1:SPBRG1 registers for the
appropriate baud rate. Set or clear the BRG16 bit,
as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
RC7/RX1/DT1
(SCKP = 0)
(SCKP = 1)
(Interrupt)
RC1IF bit
CREN bit
RCREG1
SREN bit
SREN bit
Write to
EUSART SYNCHRONOUS
MASTER RECEPTION
Read
pin
EUSART Receive Register
Baud Rate Generator Register High Byte
Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
Q2
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
RC1IE
RC1IP
RC1IF
SREN
TXEN
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
—
PIC18F6310/6410/8310/8410
Preliminary
bit 2
INT0IE
TX1IF
TX1IE
TX1IP
CREN
SYNC
SCKP
Bit 4
bit 3
ADDEN
SENDB
BRG16
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RC1IE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RC1IF will be set when reception
is complete and an interrupt will be generated if
the enable bit RC1IE was set.
Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG1 register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
bit 6
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
ABDEN
bit 7
RX9D
DS39635A-page 227
TX9D
RBIF
Bit 0
Q1 Q2 Q3 Q4
on Page
Values
Reset
57
59
59
59
59
59
59
60
60
59
‘0’