PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 76

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
TABLE 5-3:
DS39635A-page 74
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 3 High Byte
Capture/Compare/PWM Register 3 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
VDIRMAG
TMR0ON
CVREN
C2OUT
WCOL
IDLEN
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
IBF
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ACKSTAT
T3CCP2
CVROE
T08BIT
T1RUN
SSPOV
C1OUT
IRCF2
Bit 6
CKE
OBF
—
—
—
—
—
—
—
—
(1)
2
C™ Slave Mode. SSP Baud Rate Reload Register in I
T1CKPS1
T3CKPS1
SSPEN
ACKDT
VCFG1
ACQT2
DC1B1
DC2B1
DC3B1
IRVST
C2INV
IRCF1
CVRR
T0CS
CHS3
IBOV
Bit 5
D/A
—
—
PSPMODE
T1CKPS0
T3CKPS0
HLVDEN
ACKEN
CVRSS
VCFG0
ACQT1
DC1B0
DC2B0
DC3B0
IRCF0
C1INV
CHS2
T0SE
Bit 4
CKP
—
RI
P
Preliminary
T1OSCEN
CCP1M3
CCP2M3
CCP3M3
T3CCP1
HLVDL3
SSPM3
PCFG3
ACQT0
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
TO
—
—
S
TMR2ON
CCP1M2
CCP2M2
CCP3M2
T1SYNC
T3SYNC
HLVDL2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
PEN
CM2
R/W
PD
—
—
2
C Master Mode.
GO/DONE
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
CCP2M1
CCP3M1
HLVDL1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
Bit 1
POR
CM1
UA
—
—
 2004 Microchip Technology Inc.
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
CCP1M0
CCP2M0
CCP3M0
HLVDL0
SSPM0
PCFG0
ADCS0
T0PS0
ADON
CVR0
SCS0
Bit 0
BOR
SEN
CM0
BF
—
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
---- ---0
0q-1 11q0
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
-000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
--00 0000
--00 qqqq
0-00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 0000
--00 0000
xxxx xxxx
0000 0000
--00 0000
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
0000 ----
POR, BOR
Value on
on page:
58, 170,
58, 170,
58, 171,
58, 145
58, 145
58, 143
58, 265
58, 280
58, 151
58, 151
58, 147
58, 154
58, 154
58, 153
58, 178
58, 181
58, 254
58, 254
58, 245
58, 246
58, 247
59, 160
59, 160
59, 159
59, 160
59, 160
59, 159
59, 160
59, 160
59, 159
59, 261
59, 255
59, 157
59, 157
59, 155
59, 141
Details
50, 58,
36, 58
115
178
179
180