PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 394

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
Firmware Instructions ....................................................... 287
Flash Program Memory
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 308
H
Hardware Multiplier ............................................................ 99
High/Low-Voltage Detect ................................................. 265
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 117
I
DS39635A-page 392
2
C Mode (MSSP)
Associated Registers ................................................. 88
Operation During Code-Protect ................................. 88
Reading ...................................................................... 86
Introduction ................................................................ 99
Operation ................................................................... 99
Performance Comparison .......................................... 99
Associated Registers ............................................... 269
Characteristics ......................................................... 357
Current Consumption ............................................... 267
Effects of a Reset ..................................................... 269
Operation ................................................................. 266
Setup ........................................................................ 267
Typical Application ................................................... 268
Acknowledge Sequence Timing ............................... 202
Associated Registers ............................................... 208
Baud Rate Generator ............................................... 195
Bus Collision
Clock Arbitration ....................................................... 196
Clock Stretching ....................................................... 188
Effect of a Reset ...................................................... 203
General Call Address Support ................................. 192
I
Master Mode ............................................................ 193
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 203
Operation ................................................................. 182
Read/Write Bit Information (R/W Bit) ............... 182, 183
Registers .................................................................. 178
Serial Clock (RC3/SCK/SCL) ................................... 183
Slave Mode .............................................................. 182
Sleep Operation ....................................................... 203
Stop Condition Timing .............................................. 202
Transmission ............................................................ 183
2
C Clock Rate w/BRG ............................................. 195
During Sleep .................................................... 269
Start-up Time ................................................... 267
During a Repeated Start Condition .................. 206
During a Start Condition ................................... 204
During a Stop Condition ................................... 207
10-Bit Slave Receive Mode
7-Bit Slave Receive Mode
Operation ......................................................... 194
Reception ......................................................... 199
Repeated Start Condition Timing ..................... 198
Start Condition ................................................. 197
Transmission .................................................... 199
Transmit Sequence .......................................... 194
and Arbitration .................................................. 203
Addressing ....................................................... 182
Reception ......................................................... 183
(SEN = 1) ................................................. 188
(SEN = 1) ................................................. 188
Preliminary
ID Locations ............................................................. 271, 285
Idle Modes
INCF ................................................................................ 308
INCFSZ ............................................................................ 309
In-Circuit Debugger .......................................................... 285
In-Circuit Serial Programming (ICSP) ...................... 271, 285
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ....................................... 81, 334
Indirect Addressing ............................................................ 79
INFSNZ ............................................................................ 309
Initialization Conditions for all Registers ...................... 57–60
Instruction Cycle ................................................................ 67
Instruction Flow/Pipelining ................................................. 67
Instruction Set .................................................................. 287
PRI_IDLE ................................................................... 44
and Standard PIC18 Instructions ............................. 334
BSR ........................................................................... 83
Effect on Standard PIC18 Instructions ....................... 81
Mapping the Access Bank ......................................... 83
Clocking Scheme ....................................................... 67
ADDLW .................................................................... 293
ADDWF .................................................................... 293
ADDWF (Indexed Literal Offset mode) .................... 335
ADDWFC ................................................................. 294
ANDLW .................................................................... 294
ANDWF .................................................................... 295
BC ............................................................................ 295
BCF ......................................................................... 296
BN ............................................................................ 296
BNC ......................................................................... 297
BNN ......................................................................... 297
BNOV ...................................................................... 298
BNZ ......................................................................... 298
BOV ......................................................................... 301
BRA ......................................................................... 299
BSF .......................................................................... 299
BSF (Indexed Literal Offset mode) .......................... 335
BTFSC ..................................................................... 300
BTFSS ..................................................................... 300
BTG ......................................................................... 301
BZ ............................................................................ 302
CALL ........................................................................ 302
CLRF ....................................................................... 303
CLRWDT ................................................................. 303
COMF ...................................................................... 304
CPFSEQ .................................................................. 304
CPFSGT .................................................................. 305
CPFSLT ................................................................... 305
DAW ........................................................................ 306
DCFSNZ .................................................................. 307
DECF ....................................................................... 306
DECFSZ .................................................................. 307
Extended Instructions .............................................. 329
General Format ........................................................ 289
GOTO ...................................................................... 308
INCF ........................................................................ 308
INCFSZ .................................................................... 309
INFSNZ .................................................................... 309
IORLW ..................................................................... 310
IORWF ..................................................................... 310
LFSR ....................................................................... 311
MOVF ...................................................................... 311
MOVFF .................................................................... 312
MOVLB .................................................................... 312
MOVLW ................................................................... 313
Syntax .............................................................. 329
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