PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 400

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
DS39635A-page 398
High/Low-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 142
Parallel Slave Port (PSP) Write ............................... 141
Program Memory Read ............................................ 363
Program Memory Write ............................................ 364
PWM Output ............................................................ 165
Repeat Start Condition ............................................. 198
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 224
Slave Synchronization ............................................. 175
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 174
SPI Mode (Slave Mode, CKE = 0) ........................... 176
SPI Mode (Slave Mode, CKE = 1) ........................... 176
Synchronous Reception
Synchronous Transmission .............................. 225, 240
Synchronous Transmission
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 366
Transition for Entry to PRI_IDLE Mode ...................... 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 44
Transition for Wake from Sleep (HSPLL) ................... 43
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 42
USART Synchronous Receive
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 372
C Bus Start/Stop Bits ............................................. 372
C Master Mode (7 or
C Master Mode (7-Bit Reception) .......................... 201
C Master Mode First Start Bit ................................ 197
C Slave Mode (10-Bit Reception, SEN = 0) .......... 186
C Slave Mode (10-Bit Reception, SEN = 1) .......... 191
C Slave Mode (10-Bit Transmission) ..................... 187
C Slave Mode (7-bit Reception, SEN = 0) ............. 184
C Slave Mode (7-Bit Reception, SEN = 1) ............ 190
C Slave Mode (7-Bit Transmission) ....................... 185
C Slave Mode General Call Address
C Stop Condition Receive or
(VDIRMAG = 0) ................................................ 267
10-Bit Transmission) ........................................ 200
Sequence (7 or 10-Bit Address Mode) ............. 192
Transmit Mode ................................................. 202
Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 365
V
(Master Mode, SREN) .............................. 227, 242
(Through TXEN) ....................................... 226, 241
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 281
PRI_RUN Mode ................................................. 42
PRI_RUN Mode (HSPLL) .................................. 41
(Master/Slave) .................................................. 376
DD
Rise > T
2
2
C Bus Data ........................................ 374
C Bus Start/Stop Bits ........................ 374
PWRT
DD
DD
) ............................................ 55
) ........................................... 55
, V
DD
DD
DD
, Case 1) ....................... 54
, Case 2) ....................... 54
Rise T
DD
,
PWRT
) .............. 54
Preliminary
Timing Diagrams and Specifications
Top-of-Stack Access .......................................................... 64
TRISE Register
TSTFSZ ........................................................................... 327
Two-Speed Start-up ................................................. 271, 281
Two-Word Instructions
TXSTA1 Register
TXSTA2 Register
V
Voltage Reference Specifications .................................... 356
W
Watchdog Timer (WDT) ........................................... 271, 279
WCOL ...................................................... 197, 198, 199, 202
WCOL Status Flag ................................... 197, 198, 199, 202
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 327
XORWF ........................................................................... 328
USART Synchronous Transmission
A/D Conversion Requirements ................................ 378
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ........................... 362, 363
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 360
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 361
Program Memory Write Requirements .................... 364
Reset, Watchdog Timer, Oscillator
Timer0 and Timer1 External
USART Synchronous Receive
USART Synchronous Transmission
PSPMODE Bit .......................................................... 140
Example Cases .......................................................... 68
BRGH Bit ................................................................. 213
BRGH Bit ................................................................. 234
Associated Registers ............................................... 280
Control Register ....................................................... 279
During Oscillator Failure .......................................... 282
Programming Considerations .................................. 279
2
2
C Bus Data Requirements (Slave Mode) .............. 373
C Bus Start/Stop Bits Requirements
(Master/Slave) ................................................. 376
Internal RC Accuracy ....................................... 361
(All CCP Modules) ........................................... 367
(Master Mode, CKE = 0) .................................. 368
(Master Mode, CKE = 1) .................................. 369
(Slave Mode, CKE = 0) .................................... 370
(CKE = 1) ......................................................... 371
(Slave Mode) ................................................... 372
Requirements .................................................. 374
Start-up Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 365
Clock Requirements ........................................ 366
Requirements .................................................. 376
Requirements .................................................. 376
2
2
C Bus Data Requirements ................ 375
C Bus Start/Stop Bits
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