PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 256

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
19.8
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
TABLE 19-2:
DS39635A-page 254
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTF
TRISF
LATF
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
Use of the CCP2 Trigger
These pins may be configured as port pins depending on the oscillator mode selected.
Read PORTF pins, Write LATF Latch
PORTF Data Direction Register
PORTF Output Data Latch
A/D Result Register High Byte
TRISA7
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register Low Byte
OSCFIE
OSCFIP
OSCFIF
PSPIF
PSPIE
PSPIP
RA7
ADFM
Bit 7
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
TRISA6
RA6
CMIF
CMIE
CMIP
ADIE
ADIP
ADIF
Bit 6
—
—
—
(1)
(1)
PORTA Data Direction Register
VCFG1
ACQT2
RC1IF
RC1IE
RC1IP
CHS3
Bit 5
RA5
—
—
—
VCFG0
ACQT1
INT0IE
Preliminary
TX1IF
TX1IE
TX1IP
CHS2
Bit 4
RA4
—
—
—
PCFG3
ACQT0
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
CHS1
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
RBIE
Bit 3
RA3
ACQ
time selected before the “special event trigger”
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
PCFG2
ADCS2
CHS0
Bit 2
RA2
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
PCFG1
ADCS1
INT0IF
Bit 1
 2004 Microchip Technology Inc.
RA1
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
on Page
Values
Reset
57
59
59
59
59
59
59
58
58
58
58
58
60
60
60
60
60