PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 230

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
17.4
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK1 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
17.4.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG1 and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 17-9:
DS39635A-page 228
INTCON
PIR1
PIE1
IPR1
RCSTA1
TXREG1
TXSTA1
BAUDCON1 ABDOVF
SPBRGH1
SPBRG1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG1
register.
Flag bit TX1IF will not be set.
When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit TX1IF will now be set.
If enable bit TX1IE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous Slave Mode
EUSART SYNCHRONOUS SLAVE
TRANSMIT
EUSART Transmit Register
Baud Rate Generator Register High Byte
Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
TMR0IE
RC1IF
RC1IE
RC1IP
SREN
TXEN
Bit 5
—
Preliminary
INT0IE
TX1IE
TX1IP
CREN
SYNC
TX1IF
SCKP
Bit 4
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TX1IE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG1x register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
 2004 Microchip Technology Inc.
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
on Page
Values
Reset
57
59
59
59
59
59
59
60
60
59