PIC18F24J10-I/SP Microchip Technology, PIC18F24J10-I/SP Datasheet - Page 323

• Manufacturer Part Number: PIC18F24J10-I/SP
• Description: IC PIC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F24J10-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 24-5:
TABLE 24-9:
© 2009 Microchip Technology Inc.
10
11
12
13
14
15
16
17
18
18A
19
20
21
22†
23†
Param
No.
Note:
(Output)
I/O pin
(Input)
I/O pin
OSC1
CLKO
† These parameters are asynchronous events not related to any internal clock edges.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OS
OS
CK
CK
CK
CK
OS
OS
Symbol
IO
IO
IO
IO
INP
RBP
V2
V2
R
F
H2
H2
R
F
L2
H2
H2
H2
Refer to Figure 24-3 for load conditions.
CK
OS
IO
CK
IO
CK
IO
IO
V CLKO ↓ to Port Out Valid
I
H Port In Valid before CLKO ↑
V OSC1 ↑ (Q1 cycle) to Port Out Valid
I
H Port Input Valid to OSC1 ↑
H OSC1 ↑ to CLKO ↑
L OSC1 ↑ to CLKO ↓
CLKO AND I/O TIMING REQUIREMENTS
CLKO Rise Time
CLKO Fall Time
Port In Hold after CLKO ↑
OSC1 ↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
(I/O in setup time)
Port Output Rise Time
Port Output Fall Time
INTx pin High or Low Time
RB<7:4> Change INTx High or Low Time
CLKO AND I/O TIMING
Old Value
Q4
Characteristic
10
13
17
14
20, 21
Q1
19
PIC18F45J10 FAMILY
0.25 T
18
Min
100
200
T
T
—
—
—
—
—
—
—
—
CY
CY
CY
0
0
+ 25
Q2
15
New Value
Typ
50
—
—
—
—
—
—
—
—
—
—
75
75
15
15
0.5 T
Max
150
200
200
CY
—
—
—
—
—
—
—
11
30
30
6
5
12
+ 20
16
DS39682E-page 321
Units Conditions
Q3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns