CDB4265 Cirrus Logic Inc, CDB4265 Datasheet - Page 25

• Manufacturer Part Number: CDB4265
• Description: BOARD EVAL FOR CS4265 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4265

• Main Purpose: Audio, CODEC
• Embedded: No
• Utilized Ic / Part: CS4265
• Primary Attributes: Stereo, 24-Bit, 192 kHz Sample Rate
• Secondary Attributes: Graphic User Interface, S/PDIF/ I2S / I2C / SPI Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4265
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1001

DS657F2
4.2.2
4.2.3
4.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven
into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See
eration, the current value of the DC offset for the each channel is frozen and this DC offset will continue to
be subtracted from the conversion result. This feature makes it possible to perform a system DC offset cal-
ibration by:
1. Running the CS4265 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS4265.
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to
tios.
SCLK/LRCK Ratio
Characteristics section for filter settling time.
MCLK
MCLK Freq Bits
“ADC High-Pass Filter Freeze (Bit 1)” on page
Figure 10. Master Mode Clocking
Table 3. Slave Mode Serial Bit Clock Ratios
÷1.5
÷1
÷2
÷3
÷4
32x, 48x, 64x, 128x
Single-Speed
000
001
010
011
100
÷256
÷128
÷64
÷4
÷2
÷1
FM Bits
00
01
10
00
01
10
Double-Speed
32x, 48x, 64x
LRCK
SCLK
Figure
Table 3
38.) is set during normal op-
10.
for required clock ra-
Quad-Speed
32x, 48x, 64x
CS4265
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