MT18HTF6472DY-40EB2 Micron Technology Inc, MT18HTF6472DY-40EB2 Datasheet - Page 9

• Manufacturer Part Number: MT18HTF6472DY-40EB2
• Description: MODULE SDRAM DDR2 512MB 240DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18HTF6472DY-40EB2

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 240-DIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 60ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11:
PDF: 09005aef80e935cd/Source: 09005aef80e934a6
HTF18C64_128_256x72D.fm - Rev. E 2/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
valid commands; Other control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
(I
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
RC =
CK =
RAS =
RP =
RAS =
CK =
DD
DD
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
t
t
t
t
t
RP (I
RC (I
RCD =
CK (I
CK (I
t
t
OUT
OUT
RAS MAX (I
RAS MAX (I
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
t
); CKE is HIGH, S# is HIGH between valid commands; Address
),
DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
RCD (I
); CKE is LOW; Other control and address
),
t
t
RAS =
DD
RC =
), AL = 0;
Notes:
DD
DD
DD
t
),
),
DD
RC (I
t
); CKE is HIGH, S# is HIGH between valid commands;
RAS MIN (I
t
t
DD
RP =
RP =
t
CK =
Specifications and Conditions – 1GB
), AL = 0;
DD
1. Value calculated as one module rank in this operating condition, all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
t
CK =
),
t
t
RP (I
RP (I
t
CK (I
t
I
RRD =
DD
DD
t
2P (CKE LOW) mode.
DD
DD
CK (I
512MB, 1GB, 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
DD
DD
t
DD
); CKE is HIGH, S# is HIGH between valid
CK =
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
), AL = 0;
), AL =
); REFRESH command at every
t
RRD (I
DD
t
),
CK (I
t
RC =
t
DD
RCD (I
DD
t
),
CK =
t
),
t
t
RC (I
RCD =
CK =
t
t
DD
RAS =
CK =
t
CK =
t
CK (I
) - 1 x
DD
t
CK (I
),
t
t
t
RCD (I
OUT
CK (I
CK =
t
t
DD
DD
t
t
CK (I
RAS MAX (I
RAS =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
CK =
t
9
4W
DD
),
CK (I
= 0mA;
DD
t
),
DD
DD
CK (I
t
),
CK (I
DD
t
); CKE is
); CKE is
RAS MIN
);
t
DD
RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
);
);
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1
1
2
2
1
2
2
2
2
2
2
2
1,098 1,008
1,260 1,170
1,818 1,593 1,323 1,098
1,908 1,683 1,368 1,098
4,140 3,240 3,060 2,970
2,763 2,223 2,088 2,043
-80E
800
963
126
900
990
720
216
126
Electrical Specifications
©2003 Micron Technology, Inc. All rights reserved.
-667
873
126
810
900
630
216
126
-53E
783
918
126
720
810
540
216
990
126
-40E Units
783
873
126
630
720
450
216
810
126
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA