MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 19

• Manufacturer Part Number: MT4VDDT3264HY-335F2
• Description: MODULE DDR 256MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 780mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1231; MT4VDDT3264HY-335F2

pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
35. The voltage levels used are derived from a mini-
36. V
160
140
120
100
Figure 9: Reduced Output Pull-Down
80
60
40
20
80
70
60
50
40
30
20
10
Figure 7: Pull-Down Characteristics
0
0
0.0
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
IH
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
overshoot: V
DD
0.5
0.5
level and the referenced test load. In
Characteristics
3ns and the pulse width can not be
IH
1.0
1.0
(MAX) = V
V
V
V
OUT
OUT
OUT
(V)
(V)
(V)
1.5
1.5
DD
Q + 1.5V for a
IL
undershoot:
2.0
2.0
Minimum
Minimum
2.5
2.5
19
37. V
38.
39.
40. During initialization, V
128MB, 256MB (x64, SR) PC3200
-100
-120
-140
-160
-180
-200
-10
-20
-30
-40
-50
-60
-70
-80
-20
-40
-60
-80
Figure 10: Reduced Output Pull-Up
0
0
200-PIN DDR SDRAM SODIMM
0.0
0.0
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
Figure 8: Pull-Up Characteristics
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
DD
RPST), or begins driving (
TT
(MIN) = -1.5V for a pulse width
and V
may be 1.35V maximum during power up,
t
of series resistance is used between the V
DQSCK (MIN) +
DD
0.5
0.5
DD
/V
Characteristics
Q must track each other.
DD
Q are 0V, provided a minimum of
1.0
1.0
V
V
DD
DD
t
RPRE (MAX) condition.
t
Q - V
Q - V
RPRE begin point are not
DD
OUT
OUT
DD
t
Q, V
t
LZ (MIN) will prevail
RPRE).
(V)
(V)
1.5
+ 0.3V. Alternatively,
1.5
TT
t
DQSCK (MAX) +
, and V
©2004 Micron Technology, Inc.
3ns and the
2.0
2.0
Nominal low
Minimum
REF
must
TT
2.5
2.5