MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 13

MODULE DDR 256MB 200-SODIMM

MT4VDDT3264HY-335F2

Manufacturer Part Number
MT4VDDT3264HY-335F2
Description
MODULE DDR 256MB 200-SODIMM
Manufacturer
Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

Memory Type
DDR SDRAM
Memory Size
256MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
780mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1231
MT4VDDT3264HY-335F2
Table 12: I
DDR SDRAM component values only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 17–20; 0°C
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge; Burst =
4;
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;
Active-Precharge;
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
t
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
t
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with
auto precharge,
inputs change only during Active READ or WRITE commands
CK =
CK =
CK =
t
RC =
t
t
t
CK (MIN); DQ, DM and DQS inputs changing once per clock cyle;
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
t
RC (MIN);
IN
= V
DD
t
OUT
RC =
REF
t
t
RC =
CK =
t
t
Specifications and Conditions – 128MB Module
CK =
CK =
for DQ, DQS, and DM
= 0mA
t
RC (MIN);
t
RAS (MAX);
t
CK (MIN); I
t
t
CK (MIN); CKE = (LOW)
CK (MIN); CKE = LOW
0.2V
t
CK =
OUT
t
CK =
t
CK (MIN); Address and control
= 0mA; Address and control
t
CK (MIN); DQ, DM andDQS
t
t
REFC =
REFC = 7.8125µs
t
RC =
t
t
13
CK =
RFC (MIN)
T
t
A
RC (MIN);
128MB, 256MB (x64, SR) PC3200
+70°C; V
t
CK
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
I
I
I
I
I
I
I
SYM
DD4W
DD3N
= V
I
I
DD4R
I
DD5A
I
I
DD2P
DD2F
DD3P
DD0
DD1
DD5
DD6
DD7
DD
Q = +2.6V ±0.1V
MAX
1,040
1,040
2,040
-40B
540
740
240
160
280
860
16
24
16
©2004 Micron Technology, Inc.
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 42
20, 42
20, 42
24, 44
24, 44
20, 43
44
45
44
20
20
9

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