MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 20

MODULE DDR 256MB 200-SODIMM

MT4VDDT3264HY-335F2

Manufacturer Part Number
MT4VDDT3264HY-335F2
Description
MODULE DDR 256MB 200-SODIMM
Manufacturer
Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

Memory Type
DDR SDRAM
Memory Size
256MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
780mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1231
MT4VDDT3264HY-335F2
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
41. The current Micron part operates below the slow-
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
REF later.
DD
2N specifies the DQ, DQS, and DM to be
DD
2
F
except I
DD
2
Q
specifies the
DD
2
Q
is
20
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
49. This is the DC voltage supplied at the DRAM and
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic high or logic low.
is inclusive of all noise up to 20MHz. Any noise
above 20MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V ±100mV.
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
F
is “worst case.”
DD
2
F
, I
DD
2
N
, and I
DD
©2004 Micron Technology, Inc.
2
Q
are similar,

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