MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 4

MODULE DDR 256MB 200-SODIMM

MT4VDDT3264HY-335F2

Manufacturer Part Number
MT4VDDT3264HY-335F2
Description
MODULE DDR 256MB 200-SODIMM
Manufacturer
Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

Memory Type
DDR SDRAM
Memory Size
256MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
780mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1231
MT4VDDT3264HY-335F2
Table 5:
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
106, 107, 108, 109, 110,
11, 25, 47, 61, 133, 147,
12, 26, 48, 62, 134, 148,
99, 100, 101, 102, 105,
35, 37, 158, 160
PIN NUMBERS
118, 119, 120
111, 112, 115
116, 117
169, 183
170, 184
121
96
Pin Descriptions
WE#, CAS#, RAS#
DQS0–DQS7
CK0, CK0#,
DM0–DM7
CK1, CK1#
SYMBOL
BA0, BA1
A0–A12
CKE0
S0#
Output
Input/
TYPE
Input Command Inputs: RAS#, CAS#, and WE# (along with S#)
Input Clock: CK, CK# are differential clock inputs. All address and
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates
Input Chip Selects: S# enables (registered LOW) and disables
Input Bank Address: BA0 and BA1 define to which device bank an
Input Address Inputs: Provide the row address for ACTIVE
Input Data Write Mask. DM LOW allows WRITE operation. DM HIGH
4
define the command being entered.
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V
CKE is brought HIGH, it becomes an SSTL_2 input only.
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
blocks WRITE operation. DM lines do not affect READ
operation.
128MB, 256MB (x64, SR) PC3200
DD
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
is applied and until CKE is first brought HIGH. After
DESCRIPTION
©2004 Micron Technology, Inc.

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