MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 9

• Manufacturer Part Number: MT4VDDT3264HY-335F2
• Description: MODULE DDR 256MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 780mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1231; MT4VDDT3264HY-335F2

Table 6:
NOTE:
1.
2.
3.
4.
5.
Table 7:
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
LENGTH
BURST
SPEED
For a burst length of two, A1
element block; A0 selects the first access within the
block.
For a burst length of four, A2
element block; A0
block.
For a burst length of eight, A3
data-element block; A0
within the block.
Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
i = 8 (128MB);
i = 9 (256MB)
-40B
2
4
8
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
75
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
CL = 2
f
A0
CLOCK FREQUENCY (MHZ)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–
133
ALLOWABLE OPERATING
A1 select the first access within the
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
–
A2 select the first access
75
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
ORDER OF ACCESSES
CL = 2.5
0-1
1-0
WITHIN A BURST
–
–
Ai select the two-data-
f
Ai select the four-data-
–
Ai select the eight-
167
INTERLEAVED
133
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CL = 3
0-1
1-0
f
200
9
Operating Mode
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
COMMAND
COMMAND
COMMAND
128MB, 256MB (x64, SR) PC3200
The normal operating mode is selected by issuing a
All other combinations of values for A7–A12 are
200-PIN DDR SDRAM SODIMM
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
CK
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
READ
READ
READ
T0
T0
T0
TRANSITIONING DATA
CL = 2
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
CL = 3
T2
NOP
NOP
NOP
T2
T2
©2004 Micron Technology, Inc.
T2n
T2n
T2n
DON’T CARE
T3
NOP
NOP
NOP
T3
T3
T3n
T3n
T3n