MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 15

MODULE DDR 256MB 200-SODIMM

MT4VDDT3264HY-335F2

Manufacturer Part Number
MT4VDDT3264HY-335F2
Description
MODULE DDR 256MB 200-SODIMM
Manufacturer
Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

Memory Type
DDR SDRAM
Memory Size
256MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
780mA
Number Of Elements
4
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1231
MT4VDDT3264HY-335F2
Table 14: Capacitance
Note: 11; notes appearon pages 17–20
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12-15, 29; notes appear on pages 17–20; 0°C
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to READ with Auto Precharge command
ACTIVE to PRECHARGE command
PARAMETER
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Operating Conditions
CL = 3
CL = 2.5
CL = 2
T
A
15
+70°C; V
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
SYMBOL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DD
t
CK (2.5)
t
t
t
DQSCK
t
SYMBOL
t
t
t
t
CK (3)
CK (2)
DQSQ
DQSH
DIPW
DQSL
DQSS
t
t
t
t
t
t
MRD
t
t
QHS
t
t
DSH
t
t
t
t
RAP
t
t
DSS
t
t
IPW
RAS
t
QH
AC
CH
DH
IH
IH
DS
HP
HZ
CL
IS
IS
= V
LZ
C
C
C
F
S
F
S
IO
I1
I2
DD
Q = +2.6V ±0.1V
t
HP -
-0.70
-0.60
-0.70
MIN
0.45
0.45
0.40
0.40
1.75
0.35
0.35
0.72
0.20
0.20
7.5
0.6
0.6
0.6
0.6
2.2
10
15
40
5
6
t
QHS
t
CH,
-40B
t
CL
70,000
+0.70
+0.60
+0.70
MAX
0.55
0.55
0.40
1.28
0.50
MIN
7.5
13
13
4.0
8.0
6.0
UNITS
MAX
12.0
5.0
8.0
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
©2004 Micron Technology, Inc.
UNITS
NOTES
41, 46
41, 46
23, 27
23, 27
22, 23
16, 38
16, 38
22, 23
pF
pF
pF
26
26
27
30
12
12
12
12
31

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