IDT72P51339L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51339L6BBI8 Datasheet - Page 82

• Manufacturer Part Number: IDT72P51339L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51339L6BBI8

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 3.7ns
• Word Size: 36b
• Organization: 2Kx36x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51339L6BBI8

JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72P51339/72P51349/
72P51359/72P51369 incorporates the necessary tap controller and modified
pad cells to implement the JTAG facility.
program files for these devices.
TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
The Tap interface is a general-purpose port that provides access to the
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
Figure 71. Boundary Scan Architecture
UpdateDR
Instruction Register
Control Signals
82
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
The Standard JTAG interface consists of four basic elements:
• • • • •
• • • • •
• • • • •
• • • • •
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The Tap controller is a synchronous finite state machine that responds to
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Instruction Decode
Mux
6716 drw76
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005