IDT72P51339L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51339L6BBI8 Datasheet - Page 74

IC FLOW CTRL 36BIT 256-BGA

IDT72P51339L6BBI8

Manufacturer Part Number
IDT72P51339L6BBI8
Description
IC FLOW CTRL 36BIT 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72P51339L6BBI8

Configuration
Dual
Density
576Kb
Access Time (max)
3.7ns
Word Size
36b
Organization
2Kx36x8
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
166MHz
Supply Current
150mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72P51339L6BBI8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72P51339L6BBI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
2. Assertion: 2*RCLK + t
3. If t
Cycle:
*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs, REN is HIGH.
*C* No read occurs, REN is HIGH.
*D* No read occurs, REN is HIGH
*E* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore
*F* Q15 of device 1 is selected.
*G* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*H* Word, W0 is read from Q15 due to the FWFT operation.
*I* The PAE flag goes HIGH to show that Q15 is not almost empty.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
PAE
(Device 1)
PAE
(Device 2)
WCLK
RDADD
RADEN
RCLK
WEN
from at the almost empty boundary.
Flag Latencies:
De-assertion: t
REN
RCLK
PAE
Qout
REN
PAE will go LOW 2 RCLK cycles later.
SKEW2
HIGH-Z
is violated there will be one extra RCLK cycle.
HIGH-Z
t
CLKH
t
AS
t
QS
SKEW2
D
*A*
1
Q
+ RCLK + t
30
RAE
t
ENS
t
QH
n+1 words in Queue
t
AH
RAE
t
CLKL
*B*
t
Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode)
ENH
t
SKEW2
*C*
t
RAE
Figure 61. Almost Empty Flag Timing
*D*
t
AEHZ
t
AELZ
t
HIGH-Z
OLZ
74
*E*
t
ENS
t
A
t
t
AS
QS
n+2 words in Queue
D
1
*F*
Q
15
D
1
t
QH
Q
t
AH
t
ENH
30
W
n
*G*
1
t
A
t
RAE
COMMERCIAL AND INDUSTRIAL
D
1
Q
30
*H*
W
t
n+1
TEMPERATURE RANGES
RAE
t
A
D
2
1
Q
AUGUST 4, 2005
15
*I*
W
n+1 words in Queue
0
t
A
t
D
RAE
1
6716 drw69
Q
6716 drw68
15
W
1

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