IDT72P51339L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51339L6BBI8 Datasheet - Page 26

• Manufacturer Part Number: IDT72P51339L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51339L6BBI8

• Configuration: Dual
• Density: 576Kb
• Access Time (max): 3.7ns
• Word Size: 36b
• Organization: 2Kx36x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51339L6BBI8

TABLE 4 — WRITE ADDRESS BUS, WRADD[7:0]
STANDARD MODE OPERATION
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
trol devices can be configured up to a maximum of 8 queues which data can
be written via a common write port using the data inputs (Din), write clock
(WCLK) and write enable (WEN). The queue to be written is selected by the
address present on the write address bus (WRADD) during a rising edge on
WCLK while write address enable (WADEN) is HIGH. The state of WEN does
not impact the queue selection. The queue selection requires 4 WCLK cycle.
All subsequent data writes will be to this queue until another queue is selected.
device as opposed to Packet Mode where complete packets are written. The
write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-
Standard mode operation is defined as individual words will be written to the
Quadrant
Operation WCLK WADEN FSTR
Queue
Select
Select
PAFn
Write
Status Word
1
0
Address
0000
26
0
1
Write Queue Select, Write Operation and Full flag Operation). WADEN goes
high signaling a change of queue (clock cycle “A”). The address on WRADD
at that time determines the next queue. Data presented during each cycle, will
be written to the active queue, provided WEN is LOW. If WEN is HIGH (inactive),
data will not be written in a queue. The write port discrete full flag will update to
show the full status of the newly selected queue. Data present on the data input
bus (Din), can be written into the newly selected queue on the rising edge of
WCLK a change of queue, provided WEN is LOW and the queue is not full. If
the selected queue is full at the point of its selection, any writes to that queue will
be prevented. Data cannot be written into a full queue.
Operation, Figure 46, Write Operations in First Word Fall Through for timing
diagrams and Figure 47, Full Flag Timing in Expansion Configuration for timing
diagrams.
Changing queues requires 4 WCLK cycles on the write port (see Figure 44,
Refer to Figure 44, Write Queue Select, Write Operation and Full flag
Queue Status on PAFn Bus
Q0 : Q7 → PAF0 : PAF7
Device Select
(Compared to
ID2,1,0)
Device Select
(Compared to
ID2,1,0)
7 6 5
7 6 5
WRADD[7:0]
Write Queue Address
(2 bits = 4 Queues
3 bits = 8 Queues)
X
4 3
4
3 2 1 0
Status Word
Address
2 1 0
COMMERCIAL AND INDUSTRIAL
6716
drw11
TEMPERATURE RANGES
AUGUST 4, 2005