IDT72P51339L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51339L6BBI8 Datasheet - Page 24

IC FLOW CTRL 36BIT 256-BGA

IDT72P51339L6BBI8

Manufacturer Part Number
IDT72P51339L6BBI8
Description
IC FLOW CTRL 36BIT 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72P51339L6BBI8

Configuration
Dual
Density
576Kb
Access Time (max)
3.7ns
Word Size
36b
Organization
2Kx36x8
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
166MHz
Supply Current
150mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72P51339L6BBI8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72P51339L6BBI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
the SENI signal of the first device in a chain must be held LOW. The SENO signal
of a device should connect to the SENI of the next device in the chain. The SENO
of the final device is used to indicate that the programming of all devices is
complete. When the master device (ID=’000') SENO signal goes LOW the
internal programming is complete and queue write/read operation may begin.
Please refer to Figure 39, Parallel Programming for signal timing details.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
When Multi-Queue devices are connected in an Expansion Configuration,
Master
Device
Device Type
Expansion
Selected
Slave
Device
Programming
Serial
Figure 4. Device Programming Hierarchy
Mode Selected
Master Reset Cycle
Programming
Programming
Device
Default
24
6716 drw08
Parallel Queue
Programming
PROGRAMMING HIERARCHY
expansion device type, the desired programming mode and the device
operating mode during the master reset cycle (i.e. on the rising edge of Master
Reset (MRS)). The second stage is to set values such as PAE/PAF, number
of queues, queue depth, etc. using the programming mode (serial, parallel,
default) selected in stage 1. Refer to Figure 4, Device Programming Hierarchy.
Configuring the device is a 2 stage sequence. The first stage is to set the
(IDT Mode)
(Packet Mode)
Device Operating Mode
(FWFT Mode)
Selected
(IDT Mode)
COMMERCIAL AND INDUSTRIAL
(FIFO Mode)
TEMPERATURE RANGES
(FWFT Mode)
AUGUST 4, 2005

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