ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 90

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
Table 49. MMODE Register (Address 0xE700)
Bit
Location
1:0
2
3
4
7:5
Table 50. ACCMODE Register (Address 0xE701)
Bit
Location
1:0
3:2
5:4
6
7
Bit Mnemonic
PERSEL[1:0]
PEAKSEL[0]
PEAKSEL[1]
PEAKSEL[2]
Reserved
Bit Mnemonic
WATTACC[1:0]
VARACC[1:0]
CONSEL[1:0]
REVAPSEL
REVRPSEL
Default Value
00
1
1
1
000
Default Value
00
00
00
0
0
Description
00: Phase A selected as the source of the voltage line period measurement.
01: Phase B selected as the source of the voltage line period measurement.
10: Phase C selected as the source of the voltage line period measurement.
11: reserved. When set, the ADE7854/ADE7858/ADE7868/ADE7878 behave like PERSEL[1:0] = 00.
PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three
phases simultaneously. If more than one PEAKSEL[2:0] bits are set to 1, then the peak
measurement period indicated in the PEAKCYC register decreases accordingly because zero
crossings are detected on more than one phase.
When this bit is set to 1, Phase A is selected for the voltage and current peak registers.
When this bit is set to 1, Phase B is selected for the voltage and current peak registers.
When this bit is set to 1, Phase C is selected for the voltage and current peak registers.
Reserved. These bits do not manage any functionality.
Description
00: signed accumulation mode of the total and fundamental active powers. Fundamental
active powers are available in the ADE7878.
01: reserved. When set, the device behaves like WATTACC[1:0] = 00.
10: reserved. When set, the device behaves like WATTACC[1:0] = 00.
11: absolute accumulation mode of the total and fundamental active powers.
00: signed accumulation of the total and fundamental reactive powers. Total reactive powers
are available in the ADE7858, ADE7868, and ADE7878. Fundamental reactive powers are
available in the ADE7878. These bits are always 00 for the ADE7854.
01: reserved. When set, the device behaves like VARACC[1:0] = 00.
10: the total and fundamental reactive powers are accumulated, depending on the sign of
the total and fundamental active power: if the active power is positive, the reactive power is
accumulated as is, whereas if the active power is negative, the reactive power is accumulated
with reversed sign.
11: reserved. When set, the device behave like VARACC[1:0] = 00.
These bits select the inputs to the energy accumulation registers. IA’ , IB’ , and IC’ are IA, IB, and
IC shifted respectively by −90°. See Table 51.
00: 3-phase four wires with three voltage sensors.
01: 3-phase three wires delta connection.
10: 3-phase four wires with two voltage sensors.
11: 3-phase four wires delta connection.
0: The total active power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB), and on
Phase C triggers Bit 8 (REVAPC). This bit is always 0 for the ADE7854, ADE7858, and ADE7868.
1: The fundamental active power on each phase is used to trigger a bit in the STATUS0
register as follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB),
and on Phase C triggers Bit 8 (REVAPC).
0: The total active power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A triggers Bit 10 (REVRPA), on Phase B triggers Bit 11 (REVRPB), and on
Phase C triggers Bit 12 (REVRPC). This bit is always 0 for the ADE7854, ADE7858, and
ADE7868.
1: The fundamental active power on each phase is used to trigger a bit in the STATUS0
register as follows: on Phase A triggers Bit 10 (REVRPA), on Phase B triggers Bit 11 (REVRPB),
and on Phase C triggers Bit 12 (REVRPC).
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