ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 71

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 89 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 8-bit word.
See Table 53 for the HSDC_CFG register and descriptions for
the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 24 lists the time it takes to execute an HSDC data transfer
Table 24. Communication Times for Various HSDC Settings
HXFER[1:0]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
1
N/A means not applicable.
HSACTIVE
HSDATA
HSCLK
HSCLK
31
HSD
HSA
IAVW (32 BITS)
Figure 87. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
Figure 88. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
HGAP
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
31
IAVW (32 BITS)
0
7 HCLK CYCLES
0
31
VAWV (32 BITS)
31
HSIZE
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
VAWV (32 BITS)
1
Rev. D | Page 71 of 96
0
31
0
IBWV (32 BITS)
7 HCLK CYCLES
HCLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
for all HSDC_CFG register settings. For some settings, the
transfer time is less than 125 μs (8 kHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125 μs, the HSDC port transmits data only in the
first of two consecutive 8 kHz sampling cycles. This means it
transmits registers at an effective rate of 4 kHz.
ADE7854/ADE7858/ADE7868/ADE7878
0
31
IBWV (32 BITS)
Communication Time (μs)
64
128
77.125
154.25
119.25
238.25
28
56
33.25
66.5
51.625
103.25
36
72
43
86
66.625
133.25
0
31
CVAR (32 BITS)
0
31
CVAR (32 BITS)
0