ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 34

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit
unsigned registers with 1 LSB corresponding to 3.90625 μs
(256 kHz clock), which means a resolution of 0.0703° (360° ×
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/
256 kHz) for 60 Hz systems. The delays between phase voltages
or phase currents are used to characterize how balanced the
load is. The delays between phase voltages and currents are
used to compute the power factor on each phase as shown in
the following Equation 5:
where f
Period Measurement
The ADE7854/ADE7858/ADE7868/ADE7878 provide the
period measurement of the line in the voltage channel. Bits[1:0]
(PERSEL[1:0]) in the MMODE register select the phase voltage
used for this measurement. The period register is a 16-bit
unsigned register and updates every line period. Because of the
LPF1 filter (see Figure 41), a settling time of 30 ms to 40 ms is
associated with this filter before the measurement is stable.
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period register
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
length of the register enables the measurement of line frequencies
as low as 3.9 Hz (256 kHz/2
±1 LSB when the line is established and the measurement does
not change.
The following expressions can be used to compute the line
period and frequency using the period register:
cosφ
T
f
L
L
LINE
=
=
x
Figure 46. Delays Between Phase Voltages (Currents)
= cos
PERIOD[15:
PERIOD[15:
= 50 Hz or 60 Hz.
ANGLE2
PHASE A
256
256
⎡
⎢
⎢
⎣
ANGLEx
3 E
3 E
ANGLE0
0]
0]
+
+
ANGLE1
×
1
1
16
PHASE B
[
360
[
). The period register is stable at
sec
Hz
256
]
o
]
×
kHz
f
LINE
⎤
⎥
⎥
⎦
PHASE C
Rev. D | Page 34 of 96
(5)
(6)
(7)
Phase Voltage Sag Detection
The ADE7854/ADE7858/ADE7868/ADE7878 can be pro-
grammed to detect when the absolute value of any phase voltage
drops below a certain peak value for a number of half-line cycles.
The phase where this event takes place is identified in Bits[14:12]
(VSPHASE[x]) of the PHSTATUS register. This condition is
illustrated in Figure 47.
Figure 47 shows Phase A voltage falling below a threshold that
is set in the SAG level register (SAGLVL) for four half-line cycles
(SAGCYC = 4). When Bit 16 (SAG) in the STATUS1 register is set
to 1 to indicate the condition, Bit VSPHASE[0] in the PHSTATUS
register is also set to 1 because the event happened on Phase A
Bit 16 (SAG) in the STATUS1 register. All Bits[14:12] (VSPHASE[2],
VSPHASE[1], and VSPHASE[0]) of the PHSTATUS register (not
just the VSPHASE[0] bit) are erased by writing the STATUS1
register with the SAG bit set to 1.
The SAGCYC register represents the number of half-line cycles
the phase voltage must remain below the level indicated in the
SAGLVL register to trigger a SAG condition; 0 is not a valid
number for SAGCYC. For example, when the SAG cycle
(SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1
register is set at the end of the seventh half line cycle for which
the line voltage falls below the threshold. If Bit 16 (SAG) in
BIT 16 (SAG) IN
STATUS1[31:0]
PHSTATUS[12]
PHSTATUS[13]
VSPHASE[0] =
VSPHASE[1] =
SAGLVL[23:0]
SAGLVL[23:0]
FULL SCALE
FULL SCALE
IRQ1 PIN
SAGCYC[7:0] = 0x4
SAGCYC[7:0] = 0x4
PHASE A VOLTAGE
PHASE B VOLTAGE
Figure 47. SAG Detection
STATUS1[16] AND
PHSTATUS[12]
CANCELLED BY A
WRITE TO
STATUS1[31:0]
WITH SAG BIT SET
STATUS[16] AND
PHSTATUS[13]
SET TO 1