ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 67

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
The read operation using the I
ADE7858/ADE7868/ADE7878 is accomplished in two stages.
The first stage sets the pointer to the address of the register. The
second stage reads the content of the register.
As seen in Figure 82, the first stage initiates when the master
generates a start condition and consists in one byte representing
the address of the ADE7854/ADE7858/ADE7868/ADE7878
followed by the 16-bit address of the target register. The ADE78xx
acknowledges every byte received. The address byte is similar to
the address byte of a write operation and is equal to 0x70 (see
the I2C Write Operation section for details). After the last byte
of the register address has been sent and acknowledged by the
2
C Read Operation
S
0
S
SLAVE ADDRESS
1 1 1 0 0 0 0
0
1 1 1 0 0 0 1
SLAVE ADDRESS
A
C
K
ACKNOWLEDGE
GENERATED BY
2
15
C interface of the ADE7854/
REGISTER ADDRESS
ADE78xx
MSB 8 BITS OF
A
C
K
31
BYTE 3 (MSB)
OF REGISTER
ACKNOWLEDGE
GENERATED BY
ADE78xx
8
Figure 82. I
A
C
K
7
REGISTER ADDRESS
LSB 8 BITS OF
16
A
C
K
2
C Read Operation of a 32-Bit Register
15
Rev. D | Page 67 of 96
BYTE 2 OF
REGISTER
0
A
C
K
ADE7854/ADE7858/ADE7868/ADE7878, the second stage
begins with the master generating a new start condition followed
by an address byte. The most significant seven bits of this address
byte constitute the address of the ADE78xx, and they are equal
to 0111000b. Bit 0 of the address byte is a read/ write bit. Because
this is a read operation, it must be set to 1; thus, the first byte of
the read operation is 0x71. After this byte is received, the ADE78xx
generates an acknowledge. Then, the ADE78xx sends the value
of the register, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. Because registers can have 8, 16, or 32 bits,
after the last bit of the register is received, the master does not
acknowledge the transfer but generates a stop condition.
ACKNOWLEDGE
GENERATED BY
ADE7854/ADE7858/ADE7868/ADE7878
MASTER
8
A
C
K
7
BYTE 1 OF
REGISTER
0
A
C
K
7
OF REGISTER
BYTE 0 (LSB)
0
N
O
A
C
K
S