ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 70

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
HSDC Interface
The high speed data capture (HSDC) interface is disabled after
default. It can be used only if the ADE7854/ADE7858/ADE7868/
ADE7878 is configured with an I
of the ADE7854/ADE7858/ADE7868/ADE7878 cannot be used
simultaneously with HSDC.
Bit 6 (HSDCEN) in the CONFIG register activates HSDC when
set to 1. If Bit HSDCEN is cleared to 0, the default value, the
HSDC interface is disabled. Setting Bit HSDCEN to 1 when SPI
is in use does not have any effect. HSDC is an interface for
sending to an external device (usually a microprocessor or a
DSP) up to sixteen 32-bit words. The words represent the
instantaneous values of the phase currents and voltages, neutral
current, and active, reactive, and apparent powers. The registers
being transmitted include IAWV, VAWV, IBWV, VBWV, ICWV,
VCWV, AVA, INWV, BVA, CVA, AWATT, BWATT, CWATT,
AVAR, BVAR, and CVAR. All are 24-bit registers that are sign
extended to 32-bits (see Figure 35 for details). In the case of
ADE7854 and ADE7858, the INWV register is not available. In
its place, the HSDC transmits one 32-bit word always equal
to 0. In addition, the AVAR, BVAR, and CVAR registers are not
available in the ADE7854. In their place, the HSDC transmits
three 32-bit words that are always equal to 0.
HSDC can be interfaced with SPI or similar interfaces. HSDC is
always a master of the communication and consists of three
pins: HSA, HSD, and HSCLK. HSA represents the select signal.
It stays active low or high when a word is transmitted and it is
usually connected to the select pin of the slave. HSD sends data
to the slave and it is usually connected to the data input pin of
the slave. HSCLK is the serial clock line that is generated by the
ADE7854/ADE7858/ADE7868/ADE7878 and it is usually con-
nected to the serial clock input of the slave. Figure 86 shows the
connections between the ADE78xx HSDC and slave devices
containing an SPI interface.
The HSDC communication is managed by the HSDC_CFG
register (see Table 53). It is recommended to set the HSDC_CFG
register to the desired value before enabling the port using Bit 6
(HSDCEN) in the CONFIG register. In this way, the state of
various pins belonging to the HSDC port do not take levels incon-
sistent with the desired HSDC behavior. After a hardware reset
or after power-up, the MISO/HSD and SS /HSA pins are set high.
Bit 0 (HCLK) in the HSDC_CFG register determines the serial
clock frequency of the HSDC communication. When HCLK is
0 (the default value), the clock frequency is 8 MHz. When HCLK
is 1, the clock frequency is 4 MHz. A bit of data is transmitted
Figure 86. Connecting the ADE78xx HSDC with an SPI
ADE78xx
CF3/HSCLK
MISO/HSD
SS/HSA
2
C interface. The SPI interface
MISO
SCK
SS
SPI DEVICE
Rev. D | Page 70 of 96
for every HSCLK high-to-low transition. The slave device that
receives data from HSDC samples the HSD line on the low-to-
high transition of HSCLK.
The words can be transmitted as 32-bit packages or as 8-bit
packages. When Bit 1 (HSIZE) in the HSDC_CFG register is 0 (the
default value), the words are transmitted as 32-bit packages. When
Bit HSIZE is 1, the registers are transmitted as 8-bit packages. The
HSDC interface transmits the words MSB first.
Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between
packages when Bit 2 (HGAP) is set to 1. When Bit HGAP is cleared
to 0 (the default value), no gap is introduced between packages
and the communication time is shortest. In this case, HSIZE
does not have any influence on the communication and a data
bit is placed on the HSD line with every HSCLK high-to-low
transition.
Bits[4:3] (HXFER[1:0]) decide how many words are transmitted.
When HXFER[1:0] is 00, the default value, then all 16 words are
transmitted. When HXFER[1:0] is 01, only the words representing
the instantaneous values of phase and neutral currents and phase
voltages are transmitted in the following order: IAWV, VAWV,
IBWV, VBWV, ICWV, VCWV, and one 32-bit word that is always
equal to INWV. When HXFER[1:0] is 10, only the instantaneous
values of phase powers are transmitted in the following order:
AVA, BVA, CVA, AWATT, BWATT, CWATT, AVAR, BVAR, and
CVAR. The value, 11, for HXFER[1:0] is reserved and writing it is
equivalent to writing 00, the default value.
Bit 5 (HSAPOL) determines the polarity of HSA function of the
SS /HSA pin during communication. When HSAPOL is 0 (the
default value), HSA is active low during the communication.
This means that HSA stays high when no communication is in
progress. When the communication starts, HSA goes low and
stays low until the communication ends. Then it goes back to
high. When HSAPOL is 1, the HSA function of the SS /HSA pin
is active high during the communication. This means that HSA
stays low when no communication is in progress. When the
communication starts, HSA goes high and stays high until the
communication ends; then, it goes back to low.
Bits[7:6] of the HSDC_CFG register are reserved. Any value
written into these bits does not have any consequence on HSDC
behavior.
Figure 87 shows the HSDC transfer protocol for HGAP = 0,
HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC
interface sets a data bit on the HSD line every HSCLK high-
to-low transition and the value of Bit HSIZE is irrelevant.
Figure 88 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 32-bit word.