ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 76

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
Address
0x43A3
0x43A4
0x43A5
0x43A6
0x43A7
0x43A8
0x43A9
0x43AA
0x43AB
0x43AC
0x43AD
0x43AE
0x43AF
0x43B0
0x43B1
0x43B2
0x43B3
0x43B4
0x43B5
0x43B6
0x43B7
0x43B8
Register
Name
AFVARGAIN
AFVAROS
BFVARGAIN
BFVAROS
CFVARGAIN,
CFVAROS
VATHR1
VATHR0
WTHR1
WTHR0
VARTHR1
VARTHR0
Reserved
VANOLOAD
APNOLOAD
VARNOLOAD
VLEVEL
Reserved
DICOEFF
HPFDIS
Reserved
ISUMLVL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
R/W
R/W
R/W
N/A
R/W
R/W
N/A
R/W
4
4
4
1
Bit
Length
24
24
24
24
24
24
24
24
24
24
24
24
N/A
24
24
24
24
N/A
24
24
N/A
24
4
4
4
Bit Length During
Communication
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
N/A
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
N/A
32 ZPSE
32 ZP
N/A
32 ZPSE
4
4
4
Rev. D | Page 76 of 96
2
Type
S
S
S
S
S
S
U
U
U
U
U
U
N/A
S
S
S
S
N/A
S
U
N/A
S
4
4
4
3
Default
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x0000000
0x0000000
0x0000000
0x000000
0x000000
0x0000000
0x000000
0x000000
0x000000
Description
Phase A fundamental reactive power gain
adjust (ADE7878 only).
Phase A fundamental reactive power
offset adjust (ADE7878 only).
Phase B fundamental reactive power gain
adjust (ADE7878 only).
Phase B fundamental reactive power
offset adjust (ADE7878 only).
Phase C fundamental reactive power gain
adjust (ADE7878 only).
Phase C fundamental reactive power
offset adjust (ADE7878 only).
Most significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
Less significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
Most significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
Less significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
Most significant 24 bits of VARTHR[47:0]
threshold used in phase total/fundamental
reactive power datapath (ADE7858,
ADE7868, ADE7878 only).
Less significant 24 bits of VARTHR[47:0]
threshold used in phase total/fundamental
reactive power datapath (ADE7858,
ADE7868, ADE7878 only).
This memory location should be kept at
0x000000 for proper operation.
No load threshold in the apparent power
datapath.
No load threshold in the total/fundamental
active power datapath.
No load threshold in the total/fundamental
reactive power datapath. Location
reserved for ADE7854.
Register used in the algorithm that
computes the fundamental active and
reactive powers (ADE7878 only).
This location should not be written for
proper operation.
Register used in the digital integrator
algorithm. If the integrator is turned on, it
must be set at 0xFF8000. In practice, it is
transmitted as 0xFFF8000.
Disables/enables the HPF in the current
datapath (see Table 34).
This memory location should be kept at
0x000000 for proper operation.
Threshold used in comparison between
the sum of phase currents and the neutral
current (ADE7868 and ADE7878 only).