MT48V8M32LFB5-8 IT TR Micron Technology Inc, MT48V8M32LFB5-8 IT TR Datasheet - Page 6

IC SDRAM 256MBIT 125MHZ 90VFBGA

MT48V8M32LFB5-8 IT TR

Manufacturer Part Number
MT48V8M32LFB5-8 IT TR
Description
IC SDRAM 256MBIT 125MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48V8M32LFB5-8 IT TR

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
256M (8Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1107-2
Figure 1: Functional Block Diagram 8 Meg x 32 SDRAM
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
BA0, BA1
A0-A11,
RAS#
CAS#
WE#
CKE
CLK
CS#
14
ADDRESS
REGISTER
MODE REGISTER
CONTROL
LOGIC
12
speed, fully random access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless high-speed, random-access
operation.
The 256Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V low-power memory
systems. An auto refresh mode is provided, along with a power-saving, deep power-
down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle dur-
ing a burst access.
COUNTER
REFRESH
12
9
2
12
ADDRESS
2
ROW-
MUX
COUNTER/
CONTROL
COLUMN-
ADDRESS
LATCH
BANK
LOGIC
12
DECODER
ADDRESS
BANK0
LATCH
ROW-
&
9
6
4096
READ DATA LATCH
DQM MASK LOGIC
SENSE AMPLIFIERS
(4,096 x 512 x 32)
WRITE DRIVERS
I/O GATING
DECODER
COLUMN
MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK0
ARRAY
4096
(x32)
512
BANK1
BANK2
BANK3
BA1
0
0
1
1
256Mb: x32 Mobile SDRAM
32
32
4
BA0
0
1
0
1
General Description
©2003 Micron Technology, Inc. All rights reserved.
REGISTER
REGISTER
OUTPUT
DATA
DATA
INPUT
Bank
0
1
2
3
4
32
DQM0,
DQM3
DQ0-
DQ31

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