MT48V8M32LFB5-8 IT TR Micron Technology Inc, MT48V8M32LFB5-8 IT TR Datasheet - Page 40

• Manufacturer Part Number: MT48V8M32LFB5-8 IT TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48V8M32LFB5-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1107-2

WRITE with Auto Precharge
Figure 29: WRITE With Auto Precharge Interrupted by a READ
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Note:
Note:
Internal
States
Internal
States
3. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
rupt a WRITE on bank n when registered, with the data-out appearing CAS latency
later. The precharge to bank n will begin after
READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m (Figure 29).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 30).
DQM is LOW.
DQM is LOW.
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
t
WR is met, where
CLK
CLK
DQ
DQ
Page Active
Page Active
T0
NOP
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
D
T1
D
a
a
IN
IN
t
WR begins when the WRITE to bank m is registered. The last
WRITE with Burst of 4
WRITE with Burst of 4
40
a + 1
a + 1
T2
T2
D
D
NOP
NOP
IN
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
READ - AP
a + 2
T3
COL d
T3
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
t
WR - BANK n
READ with Burst of 4
t
WR is met, where
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
D
NOP
CL = 3 (bank m)
d
t
IN
Interrupt Burst, Write-Back
WR - BANK n
256Mb: x32 Mobile SDRAM
WRITE with Burst of 4
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
©2003 Micron Technology, Inc. All rights reserved.
T6
T6
t
d + 2
WR begins when the
D
NOP
D
NOP
OUT
t RP - BANK n
d
IN
Precharge
DON’T CARE
DON’T CARE
Operation
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
t RP - BANK m
OUT
IN
Write-Back