MT48V8M32LFB5-8 IT TR Micron Technology Inc, MT48V8M32LFB5-8 IT TR Datasheet - Page 32

• Manufacturer Part Number: MT48V8M32LFB5-8 IT TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48V8M32LFB5-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1107-2

Figure 17: WRITE Burst
Figure 18: WRITE to WRITE
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Note:
Note:
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a
different bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 19 on page 33. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRE-
CHARGE command to the same bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued
which the last desired input data element is registered. The auto precharge mode
requires a
BL = 2. DQM is LOW.
DQM is LOW. Each WRITE command may be to any bank.
t
WR of at least one clock plus time, regardless of frequency.
COMMAND
ADDRESS
COMMAND
CLK
ADDRESS
DQ
32
CLK
DQ
WRITE
BANK,
COL n
T0
D
n
IN
WRITE
BANK,
COL n
D
T0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
IN
NOP
n + 1
T1
D
IN
n + 1
NOP
T1
D
IN
NOP
T2
DON’T CARE
256Mb: x32 Mobile SDRAM
WRITE
BANK,
COL b
T2
D
b
IN
DON’T CARE
t
WR after the clock edge at
T3
NOP
©2003 Micron Technology, Inc. All rights reserved.
Operation