MT48V8M32LFB5-8 IT TR Micron Technology Inc, MT48V8M32LFB5-8 IT TR Datasheet - Page 42

• Manufacturer Part Number: MT48V8M32LFB5-8 IT TR
• Description: IC SDRAM 256MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48V8M32LFB5-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1107-2

Table 9: Truth Table – Current State Bank n, Command To Bank n
PDF: 09005aef80d460f2/Source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. G 6/05
Current State
Write (Auto
Row Active
Read (Auto
Precharge
Precharge
Disabled)
Disabled)
Any
Idle
Notes: 1–6; notes appear below table
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes: 1. This table applies when CKE
RAS# CAS# WE# COMMAND (ACTION)
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank.
t
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
Idle: The bank has been precharged, and
Row active: A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet ter-
minated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should
be issued on any clock edge occurring during these states. Allowable commands to the
other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when
met. Once
Row activating: Starts with registration of an ACTIVE command and ends when
met. Once
Read w/auto precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when
be in the idle state.
Write w/auto precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when
be in the idle state.
XSR has been met (if the previous state was self refresh).
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
t
t
RP is met, the bank will be in the idle state.
RCD is met, the bank will be in the row active state
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
DEEP POWER DOWN
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
DEEP POWER-DOWN
42
n-1
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RP has been met. Once
RP has been met. Once
t
RP has been met.
n
is HIGH (see Truth Table 2) and after
256Mb: x32 Mobile SDRAM
t
RCD has been met. No data
©2003 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank will
RP is met, the bank will
Truth Tables
Notes
11
10
10
10
10
10
10
t
7
7
8
8
9
9
8
9
9
t
RCD is
RP is