C8051F530-IMR Silicon Labs, C8051F530-IMR Datasheet - Page 89

• Manufacturer Part Number: C8051F530-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C
• Manufacturer: Silicon Labs

Specifications of C8051F530-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: QFN EP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

SFR Definition 8.5. ACC: Accumulator
SFR Definition 8.6. B: B Register
8.3. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Defini-
tion 8.7 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil-
lators lowers power consumption considerably; however a reset is required to restart the MCU.
The C8051F52x/F52xA/F53x/F53xA devices feature a low-power SUSPEND mode, which stops the inter-
nal oscillator until a wakening event occurs. See Section “14.1.1. Internal Oscillator Suspend Mode” on
page 136 for more information.
Bits7–0: ACC: Accumulator.
Bits7–0: B: B Register.
ACC.7
R/W
R/W
B.7
Bit7
Bit7
This register is the accumulator for arithmetic operations.
This register serves as a second accumulator for certain arithmetic operations.
ACC.6
R/W
R/W
B.6
Bit6
Bit6
ACC.5
R/W
R/W
B.5
Bit5
Bit5
ACC.4
R/W
R/W
B.4
Bit4
Bit4
Rev. 1.4
ACC.3
R/W
R/W
B.3
Bit3
Bit3
ACC.2
R/W
R/W
Bit2
B.2
Bit2
C8051F52x/F53x
ACC.1
R/W
R/W
B.1
Bit1
Bit1
SFR Address: 0xE0
SFR Address: 0xF0
ACC.0
R/W
R/W
B.0
Bit0
Bit0
00000000
Addressable
Reset Value
00000000
Addressable
Reset Value
Bit
Bit
89