C8051F530-IMR Silicon Labs, C8051F530-IMR Datasheet - Page 104

• Manufacturer Part Number: C8051F530-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C
• Manufacturer: Silicon Labs

Specifications of C8051F530-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: QFN EP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
10.5. External Interrupts
The INT0 and INT0 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT0 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “18.1. Timer 0 and Timer 1” on page 182) select level or
edge sensitive. The table below lists the possible configurations.
INT0 and INT0 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 10.5). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT0
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT0, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “13.1. Priority Crossbar
Decoder” on page 122 for complete details on configuring the Crossbar).
In the typical configuration, the external interrupt pins should be skipped in the crossbar and configured as
open-drain with the pin latch set to 1. See Section “13. Port Input/Output” on page 120 for more informa-
tion.
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT0 external inter-
rupts, respectively. If an INT0 or INT0 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
104
IT0
1
1
0
0
IN0PL
0
1
0
1
Active high, edge sensitive
Active high, level sensitive
Active low, edge sensitive
Active low, level sensitive
INT0 Interrupt
Rev. 1.4
IT1
1
1
0
0
IN1PL
0
1
0
1
Active high, edge sensitive
Active high, level sensitive
Active low, edge sensitive
Active low, level sensitive
INT1 Interrupt