C8051F530-IMR Silicon Labs, C8051F530-IMR Datasheet - Page 52

• Manufacturer Part Number: C8051F530-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C
• Manufacturer: Silicon Labs

Specifications of C8051F530-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: QFN EP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
4. 12-Bit ADC (ADC0)
The ADC0 on the C8051F52x/F52xA/F53x/F53xA Family consists of an analog multiplexer (AMUX0) with
16/6 total input selections, and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with inte-
grated track-and-hold, programmable window detector, programmable gain, and hardware accumulator.
The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accu-
mulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0,
data conversion modes, and window detector are all configurable under software control via the Special
Function Registers shown in Figure 4.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P1.7, the Temperature Sensor output, V
the ADC is selected as described in Section “5. Voltage Reference” on page 72. ADC0 is enabled when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
4.1. Analog Multiplexer
AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0–
P1.7, the on-chip temperature sensor, the core power supply (V
ended and all signals measured are with respect to GND. The ADC0 input channels are selected using
the ADC0MX register as described in SFR Definition 4.4.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN (for n = 0,1). To force the Crossbar to skip a Port
pin, set to 1 the corresponding bit in register PnSKIP (for n = 0,1). See Section “13. Port Input/Output” on
page 120 for more Port I/O configuration details.
52
*Available on ‘F53x/’F53xA
devices
P0.6*
P0.7*
P1.0*
P1.7*
P0.0
Temp Sensor
GND
VDD
Figure 4.1. ADC0 Functional Block Diagram
AMUX0
19-to-1
ADC0MX
ADC0GNH
25 MHz Max
Burst Mode
Oscillator
Selectable
Gain
Conversion
ADC0GNL
SYSCLK
Start
DD
, or GND with respect to GND. The voltage reference for
Rev. 1.4
Burst Mode
ADC0GNA
ADC0TK
Logic
ADC0CF
ADC
12-Bit
SAR
ADC0GTH ADC0GTL
ADC0LTH
VDD
DD
), or ground (GND). ADC0 is single-
ADC0CN
ADC0LTL
Conversion
Start
00
01
10
11
32
Accumulator
AD0WINT
Compare
Timer 1 Overflow
AD0BUSY (W)
CNVSTR Input
Timer 2 Overflow
Window
Logic