C8051F530-IMR Silicon Labs, C8051F530-IMR Datasheet - Page 123

• Manufacturer Part Number: C8051F530-IMR
• Description: 8-bit Microcontrollers - MCU 8KB 12ADC 125C
• Manufacturer: Silicon Labs

Specifications of C8051F530-IMR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: QFN EP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

(F52x/F52xA) for the external CNVSTR signal, and any selected ADC or comparator inputs. The Crossbar
skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 13.3
shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP); Figure 13.4 shows the
Crossbar Decoder priority with the XTAL1 (P1.0) and XTAL2 (P1.1) pins skipped (P1SKIP = 0x03).
Important Note on UART Pins: On C8051F52xA/F52x-C/F53xA/F53x-C devices, the UART pins must be
skipped if the UART is enabled in order for peripherals to appear on port pins beyond the UART on the
crossbar. For example, with the SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the
UART pins must be skipped using P0SKIP for the SPI pins to appear correctly.
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
Note: 4-Wire SPI Only.
TSSOP 20 and QFN 20
PIN I/O
TX0
RX0
TX0
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN-RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
SF Signals
Port pin potentially assignable to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
0
0
(TSSOP 20 and QFN 20)
1
0
P0SKIP[0:7] = 0x80
2
0
3
0
P0
Rev. 1.4
4
0
5
0
6
0
7
1
0
1
1
0
P1SKIP[0:7] = 0x01
C8051F53xA/F53x-C
C8051F53x devices
2
0
C8051F52x/F53x
3
0
devices
P1
4
0
5
0
6
0
7
0
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