DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 98

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

Table 11-8. Parallel CPU Interface Timing
(VDD18 = 1.8V ±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T
(See
Figure
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Setup Time for A[10:0] Valid to
Setup Time for
Delay Time from
Handshake
Delay Time from RDY or ACK Active to D[15:0] Valid
Hold Time from
Delay from
Wait Time from
Handshake
Wait Time from RDY or ACK Active to Latch D[15:0]
D[15:0] Setup Time to
D[15:0] Hold Time from
A[10:0] Hold Time from
Delay from
RD
Muxed Address Valid to ALE Inactive (Note 4)
Muxed Address Hold Time from ALE Inactive (Note 4)
ALE Pulse Width (Note 4)
Setup Time for ALE High or Muxed Address Valid to
(Notes 4, 5, 6)
Delay from
Delay from
Delay from
Delay from
,
WR
Figure
11-10.)
D[15:0] loaded with 50pF when tested as outputs.
If a gapped clock is applied on TCLK and local loopback is enabled, read cycle time must be extended by the length of the largest
TCLK gap.
Not tested during production test.
In nonmultiplexed bus applications
11-7
t14 starts at the occurrence of the rising edge of ALE or A[10:0] valid whichever occurs later.
In order to avoid bus contention, during a read cycle A[10:0] should be disabled prior to
RDY/ACK
, or
CS
WR
CS
CS
CS
CS
DS
to
11-3,
Figure
,
, RD ,
,
Inactive to D[15:0] Disable
Active to RDY/ ACK Enable
Inactive to RDY/ ACK Disable
CS
Inactive Time
RD
WR
RD
may be disabled (t18) before going inactive (t17).
RD
RD
Figure
, or
Active to
,
, or
11-10), A[10:0] should be wired to D[15:0] and the falling edge of ALE latches the address.
or
WR
WR
or
WR
DS
DS
DS
DS
, or
WR
, or
WR
Active to Latch D[15:0] Without RDY/ ACK
Inactive to D[15:0] Invalid (Note 3)
11-4,
or
Inactive to ALE Active
Active to D[15:0] Valid Without RDY/ ACK
,
DS
DS
or
RD
PARAMETER
RD
DS
DS
Inactive to RDY/ ACK Inactive (Note 7)
RD
,
Inactive to
, or
WR
Figure
Inactive
Inactive
,
DS
WR
(Figure 11-3
, or
, or
Inactive
DS
11-5,
CS
DS
Active
Inactive
to
Active (Notes 1, 2)
Figure
Figure
98 of 130
CS
11-6), ALE should be wired high. In multiplexed bus applications
11-6,
Active
Figure
11-7,
A
= -40°C to +85°C.)
SYMBOL MIN TYP MAX
Figure
t3a
t3b
t6a
t6b
t9a
t9b
t10
t11
t12
t13
t14
t15
t16
t17
t18
t1
t2
t4
t5
t7
t8
RD
or
11-8,
DS
DS32506/DS32508/DS32512
65
10
20
75
10
10
20
20
being active.
0
0
0
2
2
5
0
2
Figure
11-9, and
65
20
15
15
15
UNITS
(Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns