DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 25

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

1s where the polarity of the first 1 is opposite the polarity of the BPV in the last B3ZS/HDB3 codeword. The first 1 is
transmitted according to the normal AMI rule, but the second 1 is transmitted with the same polarity as the first 1,
thus making the second 1 a bipolar violation.
If the transmitter is configured for binary interface format (Section 8.2.2.2) and EXZI = 1, then when the configured
manual error insert control goes from zero to one, the transmitter waits for the next occurrence of three (four)
consecutive zeros in the transmit data stream and inhibits the replacement of those zeros with a B3ZS (HDB3)
codeword.
The transmitter ensures that there is at least one intervening 1 between consecutive BPV or EXZ errors. If a
second error insertion request of a given type (BPV or EXZ) is initiated before a previous request has been
completed, the second request is ignored.
8.2.4 AIS Generation
The transmitter can be configured to transmit an AIS signal by asserting the
configuration bit. The type of AIS signal to be generated is specified by the LIU mode
PORT.CR2:LM[1:0] configuration bits) and the AIS type
AIST = 0, the AIS signal is unframed all ones for DS3, E3 and STS-1 modes. When AIST = 1, the AIS signal is the
framed DS3 AIS signal in DS3 mode, unframed all ones in E3 mode, and the AIS-L signal in STS-1 mode. The
AIS-L signal is normally scrambled, but scrambling can be disabled by setting PORT.CR3:SCRD = 1.
8.2.5
8.2.5.1
Waveshaping converts the transmit clock, positive data, and negative data signals into a single analog AMI signal
with the waveshape required for interfacing to DS3/E3/STS-1 lines.
waveform equations and template.
Figure 8-3
8.2.5.2
The transmit waveshape can be adjusted with the TWSC[19:0] bits in the
registers. These signals control the amplitude, slew rates and various other aspects of the waveform template. See
the register descriptions for further details.
8.2.6
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450 feet, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225 feet or
greater, both the
When the LBO circuitry is disabled, output pulses are driven onto the coaxial cable without any preattenuation. For
cable lengths less than 225 feet, either the
enable the LBO circuitry. When the LBO circuitry is enabled, pulses are preattenuated by the LBO circuitry before
being driven onto the coaxial cable to provide attenuation that mimics the attenuation of 225 feet of coaxial cable.
8.2.7
The transmit line driver can be disabled
deasserting the LIU.CR1:TOE configuration bit. Powering down the transmitter through the
PORT.CR1:TPD configuration bit also disables the transmit line driver.
8.2.8 Interfacing to the Line
The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75Ω) through a 1:1 isolation transformer
connected to the
device, or a combination of both.
termination is enabled (LIU.CR1:TTRE = 1) and no external termination resistors are used.
arrangement of the transformer and external termination resistors when the internal termination is disabled
(LIU.CR1:TTRE = 0). The internal termination resistor value for the transmitter is specified in LIU.CR1:TRESADJ.
Table 8-7
transformers.
Waveshaping
Line Build-Out
Line Driver
Standards-Compliant Waveshaping
Programmable Waveshaping
and
shows the E3 waveform template.
Table 8-8
TLBO
TXP
and
pin and the LIU.CR1:TLBO configuration bit should be low to disable the LBO circuitry.
specify the required characteristics of the transformer and provide a list of recommended
TXN
pins. The transmit line termination can be internal to the device, external to the
Figure 8-2
Figure 4-1
(TXP
TLBO
and
and
shows the arrangement of the transformer when the internal
TXN
Table 8-4
pin or the LIU.CR1:TLBO configuration bit should be high to
25 of 130
outputs high impedance) by deasserting the
(AIST
show the STS-1 waveform equations and template.
pin or PORT.CR3:AIST configuration bit). When
Figure 8-1
TAIS
LIU.TWSCR1
and
DS32506/DS32508/DS32512
pin or the PORT.CR3:TAIS
Table 8-2
Figure 4-2
and
(LMn[1:0]
TPD
show the DS3
LIU.TWSCR2
TOE
pin or the
shows the
pin and
pins or