DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 65

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

Bit 9: BERT Enable (BERTE). See Section 8.5.
Bit 8: BERT Direction (BERTD). See Section 8.5.
Bit 7: STS-1 Scrambling Disable (SCRD). This bit controls STS-1 scrambling when AIS-L is generated in STS-1
mode. See Section 8.2.3.
Bit 4: AIS Type (AIST). See Section 8.2.4.
Bit 3: Transmit AIS (TAIS). The type of AIS signal depends on the LIU mode (DS3, E3, or STS-1) and the
configured AIS type. See Section 8.2.4.
Bit 2: Loopback Select (LBS). This bit affects the function of the loopback mode (LBM[1:0]) bits.
Bits 1 and 0: Loopback Mode (LB[1:0]). These bits enable loopbacks. The effect of the LB = 11 decode is
controlled by the LBS configuration bit. See Section 8.6.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
0 = disable the BERT pattern generator (the pattern detector is always enabled)
1 = enable the BERT pattern generator (the pattern detector is always enabled)
0 = line direction (transmit to receive)
1 = system direction (receive to transmit)
0 = Perform scrambling
1 = Do not perform scrambling
0 = Unframed all ones
1 = Framed DS3 AIS (DS3 mode), unframed all ones (E3 mode), or AIS-L (STS-1 mode)
0 = transmit normal data
1 = transmit AIS signal
00 = No loopback
01 = Diagnostic loopback (DLB)
10 = Line loopback (LLB)
11 (LBS = 0) = Line loopback (LLB) and diagnostic loopback (DLB) simultaneously
11 (LBS = 1) = Analog loopback (ALB)
SCRD
15
—
0
7
0
14
—
—
0
0
6
PORT.CR3
Port Control Register 3
n * 80h + 04h
13
—
—
0
5
0
65 of 130
AIST
12
—
0
4
0
TAIS
11
—
0
3
0
LBS
10
—
0
2
0
DS32506/DS32508/DS32512
BERTE
9
0
1
0
LB[1:0]
BERTD
8
0
0
0