DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 31

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

(AT&T 734A or equivalent). The AGC and the equalizer work simultaneously but independently to supply a signal
of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer block automatically
handles direct (0 meters) monitoring of the transmitter output signal. The real-time receiver gain level can be read
from the
level is the level read from the
8.3.4 Clock and Data Recovery (CDR)
The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces separate clock,
positive data, and negative data signals. The CDR operates from the LIU’s reference clock. See Section
more information about reference clocks and clock selection.
The receiver locks onto the incoming signal using a clock recovery PLL. The PLL lock status is indicated in the
LIU.SR:RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and reference
clock frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state
of the RLOL status bit can cause an interrupt if enabled by LIU.SRIE:RLOLIE. Note that if the reference clock is not
present, RLOL is not set.
8.3.5 Loss-of-Signal (LOS) Detector
The receiver contains analog and digital LOS detectors. The analog LOS (ALOS) detector resides in the
AGC/equalizer block. At approximately 23dB below nominal pulse amplitude ALOS is declared by setting the
LIU.SR:ALOS status bit. A change of state of the ALOS status bit can cause an interrupt if enabled by
LIU.SRIE:ALOSIE. When ALOS is declared the CDR block forces all zeros out of the data recovery circuit, causing
digital LOS (DLOS), which is indicated by the
pin follows the LIU’s reference clock, since no clock information is being received on RXP/RXN. ALOS is cleared at
approximately 22dB below nominal pulse amplitude. When the preamp is enabled (Section 8.3.2) ALOS is declared
at approximately 37dB below nominal and cleared at approximately 36dB below nominal.
The digital LOS detector declares DLOS when it detects 192 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the
LINE.RSR:LOS status bit. DLOS is cleared when there are no EXZ occurrences over a span of 192 clock periods.
An EXZ occurrence is defined as three or more consecutive zeros in DS3 and STS-1 modes and four or more
consecutive zeros in E3 mode. The
cleared. A change of state of the LINE.RSR:LOS status bit can cause an interrupt if enabled by
LINE.RSRIE:LOSIE. DLOS is only declared when B3ZS/HDB3 decoding is enabled (LINE.RCR:RZSD = 0). When
B3ZS/HDB3 decoding is disabled in the LIU, decoding should be enabled in the neighboring DS3/E3 framer, and
DLOS should be detected and report by the framer.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 192 consecutive zeros coming out of the CDR block and clears RLOS when it counts
192 consecutive pulse intervals without excessive zero occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the
DLOS detector, as follows:
For E3 RLOS Assertion:
For E3 RLOS Clear:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or
2) The DLOS detector counts 192 consecutive zeros coming out of the CDR block and asserts
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than
2) The DLOS detector counts 192 consecutive pulse intervals without EXZ occurrences and
LIU.RGLR
equal to a signal level approximately 23dB below nominal, and mutes the data coming out of
the clock and data recovery block. (23dB below nominal is in the “tolerance range” of G.775,
where LOS may or may not be declared.)
RLOS. (192 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.)
or equal to a signal level approximately 22dB below nominal, and enables data to come out of
the CDR block. (22dB is in the “tolerance range” of G.775, where LOS may or may not be
declared.)
deasserts RLOS. (192 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.)
register. Note: When the receiver preamp is on (LIU.SR:RPAS = 1), the actual receiver gain
LIU.RGLR
RLOS
register plus 14dB.
pin and the LOS status bit are deasserted when the DLOS condition is
RLOS
RLOS
pin and the LINE.RSR:LOS status bit. During ALOS the
31 of 130
pin (if the hardware interface is enabled) and the
DS32506/DS32508/DS32512
8.7.1
RCLK
for