DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 44

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

8.8.5 Clear-On-Read And Clear-On-Write Modes
The latched status register bits can be programmed to clear on a read access or clear on a write access. The
global control register bit GLOBAL.CR2.LSBCRE specifies the method used to clear all of the latched status
registers. When LSBCRE = 0, latched status register bits are cleared when written with a 1. When LSBCRE = 1,
latched status register bits are cleared when read.
The clear-on-write mode expects the user to use the following method: read the latched status register then write a
1 to the register bits to be cleared. This method is useful when multiple software tasks use the same latched status
register. Each task can clear the bits it uses without affecting any of the latched status bits used by other tasks.
The clear-on-read mode clears all latched status bits in a register automatically when the latched status register is
read. This method works well when no more than one software task uses any single latched status register. An
event that occurs while the associated latched status register is being read results in the associated latched status
bit being set after the read is completed.
8.8.6 Global Write Mode
When GLOBAL.CR2:GWRM = 1, a write to a register of any port causes the data to be written to the same register
in all the ports on the device. In this mode register reads are not supported and result in undefined data.
8.9 SPI Serial Microprocessor Interface
When the
SPI is a widely-used master/slave bus protocol that allows a master device and one or more slave devices to
communicate over a serial bus. The DS325xx is always a slave device. Masters are typically microprocessors,
ASICs or FPGAs. Data transfers are always initiated by the master device, which also generates the
The DS325xx receives serial data on the
except when the DS325xx is transmitting data to the bus master. Note that the
proper operation of the SPI interface.
Bit Order. When
and SDO. When
and SDO. The Motorola SPI convention is MSB first.
Clock Polarity and Phase. The
and pulses high during bus transactions. When
transactions. The
the leading edge of the
on SDI on the trailing edge of the
8-10.
Device Selection. Each SPI device has its own chip-select line. To select the DS325xx, pull its
Control Word. After
MSB-first mode, the control word has the form:
where A[13:0] is the register address, R/ W is the data direction bit (1 = read, 0 = write), and BURST is the burst bit
(1 = burst access, 0 = single-byte access). In LSB-first mode, the order of the 14 address bits is reversed. In the
discussion that follows, a control word with R/ W = 1 is a read control word, while a control word with R/ W = 0 is a
write control word. Note: The address range of the DS32512 is 000h–7FFh, so A[13:11] are ignored.
Single-Byte Writes. See
BURST = 0 followed by the data byte to be written. The bus master then terminates the transaction by pulling
high.
Single-Byte Reads. See
BURST = 0. The DS325xx then responds with the requested data byte. The bus master then terminates the
transaction by pulling
Burst Writes. See
followed by the first data byte to be written. The DS325xx receives the first data byte on SDI, writes it to the
specified register, increments its internal address register, and prepares to receive the next data byte. If the master
IFSEL
pins are set to 01X the device presents an SPI interface on the
IFSEL[2:0]
IFSEL[2:0]
CPHA
Figure
CS
CS
R/ W A13 A12 A11 A10 A9 A8 A7
SCLK
is pulled low, the bus master transmits the control word during the first 16
pin sets the phase (active edge) of SCLK. When
high.
8-11. After
Figure
Figure
= 011, the register address and all data bytes are transmitted LSB first on both
= 010 the register address and all data bytes are transmitted MSB first on both
pulse and updated on
CPOL
8-11. After
8-11. After
SCLK
CS
pin defines the polarity of SCLK. When
SDI
goes low, the bus master transmits a write control word with BURST = 1
pulse and updated on
pin and transmits serial data on the
CS
CS
CPOL
goes low, the bus master transmits a write control word with
goes low, the bus master transmits a read control word with
44 of 130
SDO
= 1,
on the trailing edge. When
A6 A5 A4 A3 A2 A1 A0 BURST
SCLK
SDO
is normally high and pulses low during bus
on the following leading edge. See
CPHA
SDO
CPOL
= 0, data is latched in on
ALE
CS
DS32506/DS32508/DS32512
, SCLK, SDI, and
CPHA
pin.
pin must be wired high for
= 0,
SDO
SCLK
= 1, data is latched in
CS
is high-impedance
SCLK
pin low.
is normally low
SCLK
SDO
cycles. In
SDI
signal.
Figure
pins.
SDI
SDI
CS
on