DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 76

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 12: Jitter Attenuator Full Latched (JAFL). This bit is set when the jitter attenuator buffer is full, or when data
has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if
interrupt enables LIU.SRIE:JAFIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.4.
Bit 11: Jitter Attenuator Empty Latched (JAEL). This bit is set when the jitter attenuator buffer is empty, or when
data has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if
interrupt enables LIU.SRIE:JAEIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.4.
Bit 10: Transmit Driver Monitor Change Latched (TDML). This bit is set when the LIU.SR:TDM bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TDMIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 9: Transmit Output Failure Change Latched (TFAILL). This bit is set when the LIU.SR:TFAIL bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TFAILIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 8: Loss of Master Clock Latched (LOMCL). This bit is set when the LIU.SR:LOMC bit is set. When set, this
bit causes an interrupt if interrupt enables LIU.SRIE:LOMCIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE
are all set.
Bit 5: Receive Gain Level Change Latched (RGLCL). This bit is set when the receive gain level (LIU.RGLR:
RGL[7:0]) changes. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RGLCIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set.
Bit 4: Receive Preamp Status Change Latched (RPASL). This bit is set when the LIU.SR:RPAS bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RPASIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 3: Receive Failure Type 1 Change Latched (RFAIL1L). This bit is set when the LIU.SR:RFAIL1 bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL1IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 2: Receive Failure Type 2 Change Latched (RFAIL2L). This bit is set when the LIU.SR:RFAIL2 bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL2IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 1: Receive Loss of Lock Change Latched (RLOLL). This bit is set when the LIU.SR:RLOL bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RLOLIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 0: Analog Loss of Signal Change Latched (ALOSL). This bit is set when the LIU.SR:ALOS bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:ALOSIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
15
—
—
0
7
0
14
—
—
0
6
0
LIU.SRL
LIU Status Register Latched
n * 80h + 2Ah
RGLCL
13
—
0
5
0
RPASL
76 of 130
JAFL
12
0
4
0
RFAIL1L
JAEL
11
0
3
0
RFAIL2L
TDML
10
0
2
0
DS32506/DS32508/DS32512
TFAILL
RLOLL
9
0
1
0
LOMCL
ALOSL
8
0
0
0