DS32512NW Maxim Integrated, DS32512NW Datasheet - Page 48

• Manufacturer Part Number: DS32512NW
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512NW

• Part # Aliases: 90-32512-NW0

Table 8-16. Reset and Power-Down Sources
Register bit states: F0 = forced to 0, F1 = forced to 1, 0 = set to 0, 1 = set to 1
The reset signals in the device are asserted asynchronously and do not require a clock to put the logic into the
reset state. The control registers do not require a clock to come out of the reset state, but all other logic does
require a clock to come out of the reset state.
The port transmit power-down function (PORT.CR1:TPD) disables all the transmit clocks and powers down the
transmit LIU to minimize power consumption. The port receive power-down function (PORT.CR1:RPD) disables all
of the receive clocks and powers down the receive LIU to minimize power consumption. The one-second timer
circuit can be powered down by disabling its reference clock. The CLAD can be powered down by disabling it
(setting GLOBAL.CR2:CLAD[6:0] = 0). The global logic cannot be powered down.
After a global reset, all of the control and status registers in all ports are set to their default values and all the other
flip-flops are reset to their reset values. The global data path reset (GLOBAL.CR1:RSTDP), all the port data path
resets (PORT.CR1:RSTDP), and all the port power-down (PORT.CR1:TPD and RPD) bits are set after the global
reset. A valid initialization sequence is to clear the port power-down bits in the ports that are to be active, write to all
of the configuration registers to set them in the desired modes, then clear the GLOBAL.CR1:RSTDP and
PORT.CR1:RSTDP bits. This causes all the logic to start up in a predictable manner. The device can also be
initialized by clearing the GLOBAL.CR1:RSTDP, PORT.CR1:RSTDP, and PORT.CR1:TPD and RPD bits, then
writing to all of the configuration registers to set them in the desired modes, and then clearing all of the latched
status bits. This second initialization scheme can cause the device to operate unpredictably for a brief period of
time.
Some of the I/O pins are put into a known state at reset. At the global level, the microprocessor interface output
and I/O pins (D[15:0]) are forced into the high impedance state when the
GLOBAL.CR1:RST bit is active. The CLAD clock pins CLKA, CLKB, and
clock inputs. The general-purpose I/O pins
deasserted. At the port level, the LIU transmitter outputs
Note: Setting any of the reset (RST), data path reset (RSTDP), or power-down (TPD, RPD) bits for less than 100
ns may result in the associated circuits coming up in a random state. When a power-down bit is cleared, it takes
approximately 1ms for all of the associated circuits to power-up.
RST
PIN
0
1
1
1
1
1
1
1
1
GLOBAL.CR1
RST RSTDP RST TPD RPD RSTDP
F0
1
0
0
0
0
0
0
0
F1
F1
1
0
0
0
0
0
0
REGISTER BITS
F0
F0
0
1
0
0
0
0
0
F1
F1
F1
PORT.CR1
0
1
1
0
0
0
F1
F1
F1
0
1
0
1
0
0
(GPIOAn
F1
F1
F1
0
0
0
0
1
0
48 of 130
Global
and GPIOBn) are forced to be inputs until after the
Reset
1
1
0
0
0
0
0
0
0
TXP
and
Data Path
Global
Reset
TXN
1
0
0
0
0
0
0
1
1
are forced into a high-impedance state.
INTERNAL SIGNALS
CLKC
Reset
Port
1
1
0
1
0
0
0
0
0
RST
are forced to be the LIU reference
pin is active, but not when the
Tx Port
Power-
Down
DS32506/DS32508/DS32512
1
1
0
1
1
1
0
0
0
Rx Port
Power-
Down
1
1
0
1
1
0
1
0
0
Port Data
RST
Reset
Path
1
1
1
1
1
0
0
1
0
pin is