ZL50075GAC ZARLINK [Zarlink Semiconductor Inc], ZL50075GAC Datasheet - Page 40

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ZL50075GAC

Manufacturer Part Number
ZL50075GAC
Description
32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
21 - 20
19 - 18
17 - 16
15 - 10
8 - 4
External Read/Write Address: 40200
Reset Value: 000C000C
Bit
9
31
15
0
0
30
14
0
0
OSSRC1 - 0
OSBA1 - 0
OSBR1 - 0
ISPD4 - 0
Unused
Name
29
13
0
0
ISI
28
12
0
0
H
27
11
Output Stream Bit Advancement
Output Stream Bit Rate
Unused streams are tri-stated.
If the internal system clock is used as the clock source, all the above data rates are
available. Otherwise, the data rate cannot exceed the selected clock source’s rate.
Output Stream Clock Source Select
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Stream Inversion
For normal operation, this bit is set low.
To invert the input stream, set this bit high.
Input Sampling Point Delay
Default Sampling Point is 3/4. Adjust according to Figure on page 18.
0
0
Table 23 - Group Control Register (continued)
H
OSBA1 - 0
OSBR1 - 0
OSSRC1 - 0
26
10
- 4027F
0
0
00
01
10
00
01
10
11
11
00
01
10
11
25
ISI
0
9
H
ISPD
24
8
Zarlink Semiconductor Inc.
0
4
16.384 Mbps
32.768 Mbps
65.536 Mbps
8.192 Mbps
SToA
ZL50075
Bit Rates Per Group
ISPD
23
7
0
3
Internal System Clock
Output Timing Source
40
Non-65 Mbps
CKi0 and FPi0
ISPD
OSI
15.2 ns
22.8 ns
22
7.6 ns
Reserved
Reserved
6
2
0 ns
16.384 Mbps
32.768 Mbps
8.192 Mbps
Description
Not Used
OSBA
ISPD
SToB
21
5
1
1
OSBA
ISPD
20
4
0
0
OSBR
ISBR
19
1
3
1
OSBR
ISBR
18
0
2
0
65 Mbps
11.4 ns
3.8 ns
7.6 ns
0 ns
OSSRC
ISSRC
17
1
1
1
Data Sheet
OSSRC
ISSRC
16
0
0
0

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