ZL50075GAC ZARLINK [Zarlink Semiconductor Inc], ZL50075GAC Datasheet - Page 11

• Manufacturer Part Number: ZL50075GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
B15, B18
C12
C13
B14
A16
A15
A18
B16
Pin
B2
SIZ0-1
Name
BERR
WAIT
PWR
R/W
DTA
CS
DS
IM
Chip Select Input (5 V Tolerant Input)
Active low input used with DS to enable read and write access to
the ZL50075.
Data Strobe Input (5 V Tolerant Input)
Active low input used with CS to enable read and write access to
the ZL50075.
Read/Write Input (5 V Tolerant Input)
Input signal that controls the type of microprocessor access:
0 - Microprocessor write to the ZL50075
1 - Microprocessor read from the ZL50075
Data Transfer Acknowledge (5 V Tolerant, 3.3 V Tri-state Output
with Slew-Rate)
Active low output which indicates that a data bus transfer is
complete. An external pull-up resistor is required to hold this pin
HIGH when output is high-impedance.
Transfer Bus Error Output with Slew Rate Control (5 V Tolerant,
3.3 V Tri-state Outputs with Slew-Rate Control)
This pin goes low whenever the microprocessor attempts to access
an invalid memory space inside the device. In Motorola bus mode, if
this bus error signal is activated, the data transfer acknowledge
signal, DTA, will not be generated. In Intel bus mode, the generation
of the DTA is not affected by this BERR signal. An external pull-up
resistor is required to hold a HIGH level when output is
high-impedance.
Data Transfer Wait Output (5 V Tolerant, 3.3 V Tri-state Output
with Slew Rate)
Active low wait signal output. An external pull-up resistor is required
to hold a HIGH level when output is high-impedance.
Data Transfer Size/Upper and Lower Data Strobe Inputs (5 V
Tolerant Inputs)
Motorola mode: SIZ0 - LDS, SIZ1 - UDS.
Active low upper and lower data strobes, UDS and LDS, indicate
whether the upper byte, D15-8, and/or lower byte, D7-0, is being
transferred.
Intel mode: SIZ0 - BE0, SIZ1 - BE1.
Active low Intel type bus-enable signal BE1 and BE0 signals
Microprocessor Port Bus Mode Select (5 V Tolerant Input)
Control input:
0 = Motorola mode
1 = Intel mode
Device Reset (5 V Tolerant Schmitt-Triggered Input)
Asynchronous reset input used to initialize the ZL50075.
0 = Reset
1 = Normal
See Section 11.0, Power-up and Initialization of the ZL50075 for
detailed description of Reset state.
Zarlink Semiconductor Inc.
ZL50075
11
Description
Data Sheet