ZL50075GAC ZARLINK [Zarlink Semiconductor Inc], ZL50075GAC Datasheet - Page 24

• Manufacturer Part Number: ZL50075GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The Address Bus, A18 - 0, controls access to each 32 bit location. A0 is not used and must be connected to defined
logic level. Address bit A1 and the Data Transfer Size inputs, SIZ1 - 0, identify which bytes are being accessed.
In Motorola Bus Mode (IM = 0), SIZ1 - 0 form active low data strobe signals, consistent with UDS and LDS available
on the MC68000 and MC68302 processors, as shown in Table 6.
In Intel Bus Mode (IM = 1), SIZ1 - 0 form active low byte enable signals, consistent with BE1 and BE0 available on
the Intel i960 processor, as shown in Table 6.
In both Intel and Motorola modes, the A1 address input is used to identify the word alignment in internal memory, as
shown in Table 7.
Data bus word alignments are shown in Table 8. An example of byte addressing is given in Table 9.
Pin Name
SIZ1
SIZ0
Microprocessor
16 Bit Data Bus
1. X - Don’t Care
D15 - 8
D15 - 0
D7 - 0
Motorola Mode MC68000, MC68302
Equivalent Function
Table 5 - Example of Address and Byte Significance
Address (Hex)
IM = 0
UDS
LDS
SIZ1
40200
40201
40202
40203
A1
Table 7 - Memory Data Word Alignment
0
0
1
1
0
0
1
0
1
Table 8 - Data Bus Word Alignment
Table 6 - Byte Enable Signals
Memory Data Word Alignment
Zarlink Semiconductor Inc.
ZL50075
SIZ0
1
1
0
0
0
0
1
24
Bits 31:16
Bits 15:0
Equivalent Function
Memory/Register Bits
Intel Mode i960
Bits 31:24 (MSB)
Bits 7:0 (LSB)
Bits 23:16
Bits 15:8
IM = 1
BE1
BE0
A1
X
0
1
0
1
0
1
1
Internal 32-Bit Memory
Data Bus Bytes Enabled
or Register
No access
Bits 31:24
Bits 23:16
Bits 31:16
Bits 15:8
Bits 15:0
Bits 7:0
D15-8
D7-0
Data Sheet