ZL50075GAC ZARLINK [Zarlink Semiconductor Inc], ZL50075GAC Datasheet - Page 13

• Manufacturer Part Number: ZL50075GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
1.0
1.1
The device has 64 ST-BUS/GCI-Bus inputs (STiA0 - 31 and STiB0 - 31) and 64 ST-BUS/GCI-Bus outputs (SToA0 -
31 and SToB0 - 31). It is a non-blocking digital switch with 32,768 64 kbps channels and is capable of performing
rate conversion between groups of 2 inputs and 2 outputs. The inputs accept serial input data streams with data
rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 input groups with each group
consisting of 2 streams (‘A’ and ‘B’). Each group can be set to any of the data rates. The outputs deliver serial data
streams with data rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 output groups
with each group consisting of 2 streams (‘A’ and ‘B’). Each group can be set to any of the data rates.
By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which
can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other ST-BUS/GCI-Bus devices.
The ZL50075 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input
clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with
various data rates (8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps). The rate of the input clock is defined
by setting the CK_SEL1 - 0 pins.
A selectable Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device
to operate in various modes under different switching configurations. Users can use the microprocessor port to
perform internal register and memory read and write operations. The microprocessor port has 16 bit data bus and
17 bit address bus (in A18-0, A0 is not used, and A1 is used for word alignment). There are seven control signals
(CS, DS, R/W, DTA, WAIT, BERR and IM).
The device supports the mandatory requirements for the IEEE 1149.1 (JTAG) standard via the test port.
1.2
The ZL50075 switches 64 kbps and Nx64 kbps data and voice channels from the TDM input streams, to timeslots
in the TDM output streams. The device is non-blocking; all 32 K input channels can be switched through to the
outputs. Any input channel can be switched to any available output channel.
D10, D13, E8, E11, E14, F5,
M6, M13, N4, N9, N12, N15,
F9, F12, G4, G6, G13, G15,
H14, J5, K6, K13, L14, M5,
P8, P14, R5, R10, R13
Overview
Switch Operation
Functional Description
Pin
V
Name
DD_IO
Power Supply for the I/O: +3.3 V
Zarlink Semiconductor Inc.
ZL50075
13
Description
Data Sheet