ZL50075GAC ZARLINK [Zarlink Semiconductor Inc], ZL50075GAC Datasheet - Page 34

• Manufacturer Part Number: ZL50075GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.1.2
The Connection Memory Least Significant Byte field is provided to give a convenient alternative way to modify the
output data for a stream in message mode. In this memory address range, all of the connection memory least
significant bytes (bits 7 - 0) are available for read/write in consecutive address locations. This feature is provided for
programming convenience. It can allow higher programming bandwidth on message mode streams. For example,
one longword access to this memory space can read or set the message bytes in four consecutive connection
memory locations. Access to this memory space is big-endian, with the most significant bytes on the data bus
accessing the lower address of the connection memory. Addressing into each of the streams is illustrated in Table
15.
25 - 24
23 - 15
14 - 10
9 - 0
External Read/Write Address: 000000
Reset Value: 0000
Bit
PCF
31
15
2
0
Connection Memory LSB
PCF
GP
30
14
1
4
OCL1 - 0
Unused
GP4 - 0
Name
STCH
9 - 0
H
PCF
GP
29
13
0
3
Output Coding Law
Reserved. In normal functional mode, these bits MUST be set to zero.
Source Group Selection. These bits define the input/source group number (31 - 0)
Source Stream and Channel Selection / Message Mode Data
In connection mode (constant/variable delay), these bits define the input/source stream
and channel number, depending on the data rate.
For 65.536 Mbps, bits 9 - 0 select the input channel (0 - 1023).
For 32.768 Mbps, bits 9 - 1 select the input channel (0 - 511). Bit 0 selects stream STiA
(0) or STiB (1).
For 16.869 Mbps, bits 9 - 2 select the input channel (0 - 255). Bit 0 selects stream STiA
(0) or STiB (1). Bit 1 MUST be set to 0.
For 8.192 Mbps, bits 9 - 3 select the input channel (0 - 127). Bit 0 selects stream STiA (0)
or STiB (1). Bit 2-1 MUST be set to 00.
In message mode, bits 7 - 0 define the output data. The data is output sequentially with
bit 7 being output first. Bits 9 - 8 are not used.
V/D
GP
28
12
2
Table 14 - Connection Memory Bits (CMB) (continued)
OCL1 - 0
ICL
GP
27
H
11
1
1
00
01
10
11
ICL
GP
26
10
0
0
STCH
OCL
Zarlink Semiconductor Inc.
25
9
1
9
ZL50075
For Voice (V/D bit = 0)
STCH
µ-Law w/o Mag. Inv
OCL
24
CCITT.ITU A-Law
CCITT.ITU µ-Law
0
8
8
A-Law w/o ABI
34
STCH
23
0
7
7
Description
Output Coding Law
STCH
22
6
0
6
STCH
21
5
0
5
STCH
20
4
0
4
For Data (V/D bit = 1)
All Bits Inverted
STCH
Inverted ABI
19
3
0
3
No Code
ABI
STCH
18
0
2
2
STCH
Data Sheet
17
0
1
1
STCH
16
0
0
0