ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 9

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Exceeding the threshold of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle
and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer requalify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference. This is illustrated in Figure 4.
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL
status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode
(Holdover/Normal) of the DPLL.
HOLDOVER
current REF
REF_FAIL
timer
+32 ppm
-32 ppm
C20i Clock Accuracy
0 ppm
2.5 s
-115
-100
-96
Figure 5 - Out-of-Range Thresholds for OOR_SEL=1
-83
-75
Figure 4 - Behavior of the Dis/Requalify Timer
-64
-50
-51
C20
-32
10 s
-32
Zarlink Semiconductor Inc.
SCM or CFM failure
-25
ZL30108
C20
0
0
9
25
C20
32
32
50
51
64
75
83
96
100
115
In Range
In Range
Out of Range
In Range
Frequency offset [ppm]
Out of Range
Out of Range
Data Sheet