ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 14

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

5.0
5.1
The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the
OOR_SEL pin, see Table 2.
5.2
The ZL30108 has two possible manual modes of operation; Normal and Freerun. These modes are selected with
mode select pins MODE_SEL as is shown in Table 3. Transitioning from one mode to the other is controlled
externally.
5.2.1
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30108 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
is required, the master clock must also be
5.2.2
Normal mode is typically used when a system clock source, synchronized to the network or a backplane is required.
In Normal mode, the ZL30108 provides timing and frame synchronization signals, which are synchronized to one of
two reference inputs (REF0 or REF1). The input reference signal may have a nominal frequency of 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. The frequency of the reference inputs are
automatically detected by the reference monitors.
When the Normal mode is selected through the MODE_SEL pin, the ZL30108 will automatically go into the
Automatic Holdover mode if the currently selected reference is disrupted (see Figure 9). After the power up reset,
the ZL30108 will initially go into the Automatic Holdover mode, generating clocks with the same accuracy as it
would be in the Freerun mode. If the currently selected reference is not disrupted (see Figure 3), the state machine
takes the DPLL out of the Automatic Holdover mode. The transition is done through the TIE correction state and the
current phase offset of the output signals to the input reference is maintained.
Out of Range Selection
Modes of Operation
Control and Modes of Operation
Freerun Mode
Normal Mode
MODE_SEL
0
1
Table 2 - Out of Range Limits Selection
OOR_SEL
±
Table 3 - Operating Modes
32 ppm. See Applications - Section 7.2, “Master Clock“.
0
1
Zarlink Semiconductor Inc.
Normal (with automatic Holdover)
ZL30108
Out Of Range Limits
14
40 - 52 ppm
64 - 83 ppm
Freerun
Mode
±
32 ppm output clock
Data Sheet