ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 6

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.0
Pin #
10
12
13
14
15
16
17
18
19
20
11
1
2
3
4
5
6
7
8
9
Pin Description
MODE_SEL
REF_FAIL0
REF_FAIL1
AV
AV
V
V
AGND
Name
LOCK
OSCo
OSCi
AV
AV
GND
GND
GND
F2ko
RST
V
CORE
CORE
CORE
CORE
IC
DD
DD
DD
Ground. 0 V
Positive Supply Voltage. +1.8 V
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0
reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that
it is exhibiting abrupt phase or frequency changes.
Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1
reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that
it is exhibiting abrupt phase or frequency changes.
Positive Supply Voltage. +1.8 V
Positive Analog Supply Voltage. +1.8 V
Ground. 0 V
Mode Select (Input). This input determines the mode of operation: See Table 3.
0: Normal mode (device locked to input reference)
1: Freerun mode
Reset (Input). A logic low at this input resets the device. On power up, the RST pin must
be held low for a minimum of 300 ns after the power supply pins have reached the
minimum supply voltage. When the RST pin goes high, the device will transition into a
Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be forced
into high impedance.
Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
Internal Connection. Connect this pin to VDD.
Positive Supply Voltage. +3.3 V
Positive Analog Supply Voltage. +3.3 V
Ground. 0 V
Analog Ground. 0 V
Positive Analog Supply Voltage. +1.8 V
Positive Analog Supply Voltage. +3.3 V
Multi Frame Pulse (Output). This is a CMOS 2 kHz active high 51 ns framing pulse,
which marks the beginning of a multi frame.
This clock output pad includes a Schmitt triggered input which serves as a PLL feedback
path; proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Zarlink Semiconductor Inc.
ZL30108
6
DC
DC
DC
nominal
nominal
nominal.
Description
DC
DC
DC
DC
nominal
nominal
nominal
nominal.
Data Sheet